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gerrit.rockbox.org / rockbox / 0b6cbd8e49eaf664cd005c6bb63a3111a4f4c308 / . / utils / regtools / desc / regs-jz4760b.xml
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<?xml version="1.0"?>
<soc version="2">
<name>jz4760b</name>
<author>Amaury Pouly</author>
<isa>mips (xburst)</isa>
<version>1.0</version>
<node>
<name>IPU_P</name>
<instance>
<name>IPU_P</name>
<address>0x13080000</address>
</instance>
</node>
<node>
<name>CPM</name>
<instance>
<name>CPM</name>
<address>0xb0000000</address>
</instance>
<node>
<name>CTRL</name>
<title>Clock control register</title>
<instance>
<name>CTRL</name>
<address>0x0</address>
</instance>
<register>
<field>
<name>ECS</name>
<position>31</position>
</field>
<field>
<name>MEM</name>
<position>30</position>
</field>
<field>
<name>SDIV</name>
<position>24</position>
<width>4</width>
</field>
<field>
<name>CE</name>
<position>22</position>
</field>
<field>
<name>PCS</name>
<position>21</position>
</field>
<field>
<name>H2DIV</name>
<position>16</position>
<width>4</width>
</field>
<field>
<name>MDIV</name>
<position>12</position>
<width>4</width>
</field>
<field>
<name>PDIV</name>
<position>8</position>
<width>4</width>
</field>
<field>
<name>HDIV</name>
<position>4</position>
<width>4</width>
</field>
<field>
<name>CDIV</name>
<position>0</position>
<width>4</width>
</field>
</register>
</node>
<node>
<name>LOW</name>
<title>Low power control register</title>
<instance>
<name>LOW</name>
<address>0x4</address>
</instance>
<register>
<field>
<name>PDAHB1</name>
<position>30</position>
</field>
<field>
<name>VBATIR</name>
<position>29</position>
</field>
<field>
<name>PDGPS</name>
<position>28</position>
</field>
<field>
<name>PDAHB1S</name>
<position>26</position>
</field>
<field>
<name>PDGPSS</name>
<position>24</position>
</field>
<field>
<name>PST</name>
<position>8</position>
<width>12</width>
</field>
<field>
<name>DUTY</name>
<position>3</position>
<width>5</width>
</field>
<field>
<name>DOZE</name>
<position>2</position>
</field>
<field>
<name>LPM</name>
<position>0</position>
<width>2</width>
<enum>
<name>IDLE</name>
<value>0x0</value>
</enum>
<enum>
<name>SLEEP</name>
<value>0x1</value>
</enum>
</field>
</register>
</node>
<node>
<name>RESET</name>
<title>Reset status register</title>
<instance>
<name>RESET</name>
<address>0x8</address>
</instance>
<register>
<field>
<name>P0R</name>
<position>2</position>
</field>
<field>
<name>WR</name>
<position>1</position>
</field>
<field>
<name>PR</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>PLL0</name>
<title>PLL control register 0</title>
<instance>
<name>PL</name>
<address>0x10</address>
</instance>
<register>
<field>
<name>PLLM</name>
<position>24</position>
<width>7</width>
</field>
<field>
<name>PLLN</name>
<position>18</position>
<width>4</width>
</field>
<field>
<name>PLLOD</name>
<position>16</position>
<width>2</width>
</field>
<field>
<name>LOCK</name>
<desc>LOCK0 bit</desc>
<position>15</position>
</field>
<field>
<name>ENLOCK</name>
<position>14</position>
</field>
<field>
<name>PLLS</name>
<position>10</position>
</field>
<field>
<name>PLLBP</name>
<position>9</position>
</field>
<field>
<name>PLLEN</name>
<position>8</position>
</field>
<field>
<name>PLLST</name>
<position>0</position>
<width>8</width>
</field>
</register>
</node>
<node>
<name>PLLSWITCH</name>
<title>PLL switch and status register</title>
<instance>
<name>PLLSWITCH</name>
<address>0x14</address>
</instance>
<register>
<field>
<name>PLLOFF</name>
<position>31</position>
</field>
<field>
<name>PLLBP</name>
<position>30</position>
</field>
<field>
<name>PLLON</name>
<position>29</position>
</field>
<field>
<name>PS</name>
<position>28</position>
</field>
<field>
<name>FS</name>
<position>27</position>
</field>
<field>
<name>CS</name>
<position>26</position>
</field>
<field>
<name>SM</name>
<position>2</position>
</field>
<field>
<name>PM</name>
<position>1</position>
</field>
<field>
<name>FM</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>GATE0</name>
<title>Clock gate register 0</title>
<instance>
<name>GATE0</name>
<address>0x20</address>
</instance>
<register>
<field>
<name>EMC</name>
<position>31</position>
</field>
<field>
<name>DDR</name>
<position>30</position>
</field>
<field>
<name>IPU</name>
<position>29</position>
</field>
<field>
<name>LCD</name>
<position>28</position>
</field>
<field>
<name>TVE</name>
<position>27</position>
</field>
<field>
<name>CIM</name>
<position>26</position>
</field>
<field>
<name>MDMA</name>
<position>25</position>
</field>
<field>
<name>UHC</name>
<position>24</position>
</field>
<field>
<name>MAC</name>
<position>23</position>
</field>
<field>
<name>GPS</name>
<position>22</position>
</field>
<field>
<name>DMAC</name>
<position>21</position>
</field>
<field>
<name>SSI2</name>
<position>20</position>
</field>
<field>
<name>SSI1</name>
<position>19</position>
</field>
<field>
<name>UART3</name>
<position>18</position>
</field>
<field>
<name>UART2</name>
<position>17</position>
</field>
<field>
<name>UART1</name>
<position>16</position>
</field>
<field>
<name>UART0</name>
<position>15</position>
</field>
<field>
<name>SADC</name>
<position>14</position>
</field>
<field>
<name>KBC</name>
<position>13</position>
</field>
<field>
<name>MSC2</name>
<position>12</position>
</field>
<field>
<name>MSC1</name>
<position>11</position>
</field>
<field>
<name>OWI</name>
<position>10</position>
</field>
<field>
<name>TSSI</name>
<position>9</position>
</field>
<field>
<name>AIC</name>
<position>8</position>
</field>
<field>
<name>SCC</name>
<position>7</position>
</field>
<field>
<name>I2C1</name>
<position>6</position>
</field>
<field>
<name>I2C0</name>
<position>5</position>
</field>
<field>
<name>SSI0</name>
<position>4</position>
</field>
<field>
<name>MSC0</name>
<position>3</position>
</field>
<field>
<name>OTG</name>
<position>2</position>
</field>
<field>
<name>BCH</name>
<position>1</position>
</field>
<field>
<name>NEMC</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>OSC</name>
<title>Oscillator and power control register</title>
<instance>
<name>OSC</name>
<address>0x24</address>
</instance>
<register>
<field>
<name>O1ST</name>
<position>8</position>
<width>8</width>
</field>
<field>
<name>OTGPHY_ENABLE</name>
<desc>SPENDN bit</desc>
<position>7</position>
</field>
<field>
<name>GPSEN</name>
<position>6</position>
</field>
<field>
<name>UHCPHY_DISABLE</name>
<desc>SPENDH bit</desc>
<position>5</position>
</field>
<field>
<name>O1SE</name>
<position>4</position>
</field>
<field>
<name>PD</name>
<position>3</position>
</field>
<field>
<name>ERCS</name>
<position>2</position>
</field>
</register>
</node>
<node>
<name>GATE1</name>
<title>Clock gate register 1</title>
<instance>
<name>GATE1</name>
<address>0x28</address>
</instance>
<register>
<field>
<name>AUX</name>
<position>11</position>
</field>
<field>
<name>OSD</name>
<position>10</position>
</field>
<field>
<name>GPU</name>
<position>9</position>
</field>
<field>
<name>PCM</name>
<position>8</position>
</field>
<field>
<name>AHB1</name>
<position>7</position>
</field>
<field>
<name>CABAC</name>
<position>6</position>
</field>
<field>
<name>SRAM</name>
<position>5</position>
</field>
<field>
<name>DCT</name>
<position>4</position>
</field>
<field>
<name>ME</name>
<position>3</position>
</field>
<field>
<name>DBLK</name>
<position>2</position>
</field>
<field>
<name>MC</name>
<position>1</position>
</field>
<field>
<name>BDMA</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>PLL1</name>
<title>PLL control register 1</title>
<instance>
<name>PLL1</name>
<address>0x30</address>
</instance>
<register>
<field>
<name>PLL1M</name>
<position>24</position>
<width>7</width>
</field>
<field>
<name>PLL1N</name>
<position>18</position>
<width>4</width>
</field>
<field>
<name>PLL1OD</name>
<position>16</position>
<width>2</width>
</field>
<field>
<name>P1SCS</name>
<position>15</position>
</field>
<field>
<name>P1SDIV</name>
<position>9</position>
<width>6</width>
</field>
<field>
<name>PLL1EN</name>
<position>7</position>
</field>
<field>
<name>PLL1S</name>
<position>6</position>
</field>
<field>
<name>LOCK</name>
<desc>LOCK1 bit</desc>
<position>2</position>
</field>
<field>
<name>PLL1OFF</name>
<position>1</position>
</field>
<field>
<name>PLL1ON</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>SCRATCH</name>
<title>CPM scratch pad register</title>
<instance>
<name>SCRATCH</name>
<address>0x34</address>
</instance>
<register/>
</node>
<node>
<name>SCRATCHPROT</name>
<title>CPM scratch pad protected register</title>
<instance>
<name>SCRATCHPROT</name>
<address>0x38</address>
</instance>
<register/>
</node>
<node>
<name>USBPARAM</name>
<title>OTG parameter control register</title>
<instance>
<name>USBPARAM</name>
<address>0x3c</address>
</instance>
<register>
<field>
<name>USB_MODE</name>
<position>31</position>
</field>
<field>
<name>AVLD_REG</name>
<position>30</position>
</field>
<field>
<name>IDPULLUP</name>
<desc>IDPULLUP_MASK bit</desc>
<position>28</position>
<width>2</width>
</field>
<field>
<name>INCRM</name>
<desc>INCR_MASK bit</desc>
<position>27</position>
</field>
<field>
<name>CLK12_EN</name>
<position>26</position>
</field>
<field>
<name>COMMONONN</name>
<position>25</position>
</field>
<field>
<name>VBUSVLDEXT</name>
<position>24</position>
</field>
<field>
<name>VBUSVLDEXTSEL</name>
<position>23</position>
</field>
<field>
<name>POR</name>
<position>22</position>
</field>
<field>
<name>SIDDQ</name>
<position>21</position>
</field>
<field>
<name>OTG_DISABLE</name>
<position>20</position>
</field>
<field>
<name>COMPDISTUNE</name>
<position>17</position>
<width>3</width>
</field>
<field>
<name>OTGTUNE</name>
<position>14</position>
<width>3</width>
</field>
<field>
<name>SQRXTUNE</name>
<position>11</position>
<width>3</width>
</field>
<field>
<name>TXFSLSTUNE</name>
<position>7</position>
<width>4</width>
</field>
<field>
<name>TXPREEMPHTUNE</name>
<position>6</position>
</field>
<field>
<name>TXRISETUNE</name>
<position>4</position>
<width>2</width>
</field>
<field>
<name>TXVREFTUNE</name>
<position>0</position>
<width>4</width>
</field>
</register>
</node>
<node>
<name>USBRESET</name>
<title>OTG reset detect timer register</title>
<instance>
<name>USBRESET</name>
<address>0x40</address>
</instance>
<register>
<field>
<name>VBFIL_LD_EN</name>
<position>25</position>
</field>
<field>
<name>IDDIG_EN</name>
<position>24</position>
</field>
<field>
<name>IDDIG_REG</name>
<position>23</position>
</field>
<field>
<name>USBRDT</name>
<position>0</position>
<width>23</width>
</field>
</register>
</node>
<node>
<name>USBVBUS</name>
<instance>
<name>USBVBUS</name>
<address>0x44</address>
</instance>
<register/>
</node>
<node>
<name>USB</name>
<title>OTG PHY clock divider register</title>
<instance>
<name>USB</name>
<address>0x50</address>
</instance>
<register>
<field>
<name>UCS</name>
<position>31</position>
</field>
<field>
<name>UPCS</name>
<position>30</position>
</field>
<field>
<name>OTGDIV</name>
<desc>USBCDR bit</desc>
<position>0</position>
<width>6</width>
</field>
</register>
</node>
<node>
<name>I2S</name>
<title>I2S device clock divider register</title>
<instance>
<name>I2S</name>
<address>0x60</address>
</instance>
<register>
<field>
<name>I2CS</name>
<position>31</position>
</field>
<field>
<name>I2PCS</name>
<position>30</position>
</field>
<field>
<name>I2SDIV</name>
<desc>I2SCDR bit</desc>
<position>0</position>
<width>9</width>
</field>
</register>
</node>
<node>
<name>LCD</name>
<title>LCD pix clock divider register</title>
<instance>
<name>LCD</name>
<address>0x64</address>
</instance>
<register>
<field>
<name>LTCS</name>
<position>30</position>
</field>
<field>
<name>LPCS</name>
<position>29</position>
</field>
<field>
<name>PIXDIV</name>
<desc>LPCDR bit</desc>
<position>0</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>MSC</name>
<title>MSC clock divider register</title>
<instance>
<name>MSC</name>
<address>0x68</address>
</instance>
<register>
<field>
<name>MCS</name>
<position>31</position>
</field>
<field>
<name>MSCDIV</name>
<desc>MSCCDR bit</desc>
<position>0</position>
<width>6</width>
</field>
</register>
</node>
<node>
<name>UHC</name>
<title>UHC device clock divider register</title>
<instance>
<name>UHC</name>
<address>0x6c</address>
</instance>
<register>
<field>
<name>UHPCS</name>
<position>31</position>
</field>
<field>
<name>UHCDIV</name>
<desc>UHCCDR bit</desc>
<position>0</position>
<width>4</width>
</field>
</register>
</node>
<node>
<name>SSI</name>
<title>SSI clock divider register</title>
<instance>
<name>SSI</name>
<address>0x74</address>
</instance>
<register>
<field>
<name>SCS</name>
<position>31</position>
</field>
<field>
<name>SSIDIV</name>
<desc>SSICDR bit</desc>
<position>0</position>
<width>6</width>
</field>
</register>
</node>
<node>
<name>CIM</name>
<title>CIM mclk clock divider register</title>
<instance>
<name>CIM</name>
<address>0x7c</address>
</instance>
<register>
<field>
<name>CIMDIV</name>
<desc>CIMCDR bit</desc>
<position>0</position>
<width>8</width>
</field>
</register>
</node>
<node>
<name>GPS</name>
<title>GPS clock divider register</title>
<instance>
<name>GPS</name>
<address>0x80</address>
</instance>
<register>
<field>
<name>GPCS</name>
<position>31</position>
</field>
<field>
<name>GPSDIV</name>
<desc>GPSCDR bit</desc>
<position>0</position>
<width>4</width>
</field>
</register>
</node>
<node>
<name>PCM</name>
<title>PCM device clock divider register</title>
<instance>
<name>PCM</name>
<address>0x84</address>
</instance>
<register>
<field>
<name>PCMS</name>
<position>31</position>
</field>
<field>
<name>PCMPCS</name>
<position>30</position>
</field>
<field>
<name>PCMDIV</name>
<desc>PCMCDR bit</desc>
<position>0</position>
<width>9</width>
</field>
</register>
</node>
<node>
<name>GPU</name>
<instance>
<name>GPU</name>
<address>0x88</address>
</instance>
<register>
<field>
<name>GPCS</name>
<position>31</position>
</field>
<field>
<name>GPUDIV</name>
<desc>GPUCDR bit</desc>
<position>0</position>
<width>3</width>
</field>
</register>
</node>
<node>
<name>PSWC0ST</name>
<instance>
<name>PSWC0ST</name>
<address>0x90</address>
</instance>
<register/>
</node>
<node>
<name>PSWC1ST</name>
<instance>
<name>PSWC1ST</name>
<address>0x94</address>
</instance>
<register/>
</node>
<node>
<name>PSWC2ST</name>
<instance>
<name>PSWC2ST</name>
<address>0x98</address>
</instance>
<register/>
</node>
<node>
<name>PSWC3ST</name>
<instance>
<name>PSWC3ST</name>
<address>0x9c</address>
</instance>
<register/>
</node>
</node>
<node>
<name>INTC</name>
<title>INTC (Interrupt Controller)</title>
<instance>
<name>INTC</name>
<address>0xb0001000</address>
</instance>
<node>
<name>ISR</name>
<instance>
<name>ISR</name>
<range>
<first>0</first>
<count>2</count>
<formula variable="n">0x00 + (n) * 0x20</formula>
</range>
</instance>
<register/>
</node>
<node>
<name>IMR</name>
<instance>
<name>IMR</name>
<range>
<first>0</first>
<count>2</count>
<formula variable="n">0x04 + (n) * 0x20</formula>
</range>
</instance>
<register/>
</node>
<node>
<name>IMSR</name>
<instance>
<name>IMSR</name>
<range>
<first>0</first>
<count>2</count>
<formula variable="n">0x08 + (n) * 0x20</formula>
</range>
</instance>
<register/>
</node>
<node>
<name>IMCR</name>
<instance>
<name>IMCR</name>
<range>
<first>0</first>
<count>2</count>
<formula variable="n">0x0c + (n) * 0x20</formula>
</range>
</instance>
<register/>
</node>
<node>
<name>IPR</name>
<instance>
<name>IPR</name>
<range>
<first>0</first>
<count>2</count>
<formula variable="n">0x10 + (n) * 0x20</formula>
</range>
</instance>
<register/>
</node>
</node>
<node>
<name>OST</name>
<title>Operating System Timer</title>
<instance>
<name>OST</name>
<address>0xb0002000</address>
</instance>
<node>
<name>DATA</name>
<title>Data register</title>
<instance>
<name>DATA</name>
<address>0xe0</address>
</instance>
<register/>
</node>
<node>
<name>COUNTL</name>
<title>Count (low part)</title>
<instance>
<name>COUNTL</name>
<address>0xe4</address>
</instance>
<register/>
</node>
<node>
<name>COUNTH</name>
<title>Count (high-part)</title>
<instance>
<name>COUNTH</name>
<address>0xe8</address>
</instance>
<register/>
</node>
<node>
<name>CTRL</name>
<title>Operating system control register</title>
<instance>
<name>CTRL</name>
<address>0xec</address>
</instance>
<register>
<width>16</width>
<field>
<name>CNT_MD</name>
<position>15</position>
</field>
<field>
<name>SD</name>
<position>9</position>
</field>
<field>
<name>PRESCALE</name>
<position>3</position>
<width>3</width>
<enum>
<name>1</name>
<value>0x0</value>
</enum>
<enum>
<name>4</name>
<value>0x1</value>
</enum>
<enum>
<name>16</name>
<value>0x2</value>
</enum>
<enum>
<name>64</name>
<value>0x3</value>
</enum>
<enum>
<name>256</name>
<value>0x4</value>
</enum>
<enum>
<name>1024</name>
<value>0x5</value>
</enum>
</field>
<field>
<name>EXT_EN</name>
<position>2</position>
</field>
<field>
<name>RTC_EN</name>
<position>1</position>
</field>
<field>
<name>PCK_EN</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>COUNTH_BUF</name>
<instance>
<name>OSTCNTH_BUF</name>
<address>0xfc</address>
</instance>
<register/>
</node>
</node>
<node>
<name>TCU</name>
<title>Timer and counter unit module</title>
<instance>
<name>TCU</name>
<address>0xb0002000</address>
</instance>
<node>
<name>ENABLE</name>
<title>Timer counter enable register</title>
<instance>
<name>ENABLE</name>
<address>0x10</address>
</instance>
<register>
<width>16</width>
<field>
<name>OSTEN</name>
<position>15</position>
</field>
<field>
<name>TCEN</name>
<position>0</position>
<width>8</width>
</field>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>STOP</name>
<title>Timer stop register</title>
<instance>
<name>STOP</name>
<address>0x1c</address>
</instance>
<register>
<field>
<name>WDT_STOP</name>
<position>16</position>
</field>
<field>
<name>OST_STOP</name>
<position>15</position>
</field>
<field>
<name>TIMER_STOP</name>
<position>0</position>
<width>8</width>
</field>
<variant>
<type>set</type>
<offset>16</offset>
</variant>
<variant>
<type>clr</type>
<offset>32</offset>
</variant>
</register>
</node>
<node>
<name>FLAG</name>
<title>Timer flag register</title>
<instance>
<name>FLAG</name>
<address>0x20</address>
</instance>
<register>
<field>
<name>HFLAG</name>
<position>16</position>
<width>8</width>
</field>
<field>
<name>OSTFLAG</name>
<position>15</position>
</field>
<field>
<name>FFLAG</name>
<position>0</position>
<width>8</width>
</field>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>MASK</name>
<title>Timer mask register</title>
<instance>
<name>TMR</name>
<address>0x30</address>
</instance>
<register>
<field>
<name>HMASK</name>
<position>16</position>
<width>8</width>
</field>
<field>
<name>OSTMASK</name>
<position>15</position>
</field>
<field>
<name>FMASK</name>
<position>0</position>
<width>8</width>
</field>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>DATA_FULL</name>
<title>Timer data full register</title>
<instance>
<name>DATA_FULL</name>
<range>
<first>0</first>
<count>8</count>
<formula variable="n">(n) * 0x10 + 0x40</formula>
</range>
</instance>
<register>
<width>16</width>
<field>
<name>TDFR</name>
<position>0</position>
<width>16</width>
</field>
</register>
</node>
<node>
<name>DATA_HALF</name>
<title>Timer data half register</title>
<instance>
<name>DATA_HALF</name>
<range>
<first>0</first>
<count>8</count>
<formula variable="n">(n) * 0x10 + 0x44</formula>
</range>
</instance>
<register>
<width>16</width>
<field>
<name>TDHR</name>
<position>0</position>
<width>16</width>
</field>
</register>
</node>
<node>
<name>COUNT</name>
<title>Timer counter register</title>
<instance>
<name>COUNT</name>
<range>
<first>0</first>
<count>8</count>
<formula variable="n">(n) * 0x10 + 0x48</formula>
</range>
</instance>
<register>
<width>16</width>
<field>
<name>TCNT</name>
<position>0</position>
<width>16</width>
</field>
</register>
</node>
<node>
<name>CTRL</name>
<title>Timer control register</title>
<instance>
<name>CTRL</name>
<range>
<first>0</first>
<count>8</count>
<formula variable="n">(n) * 0x10 + 0x4c</formula>
</range>
</instance>
<register>
<width>16</width>
<field>
<name>CLRZ</name>
<position>10</position>
</field>
<field>
<name>SD_ABRUPT</name>
<position>9</position>
</field>
<field>
<name>INITL_HIGH</name>
<position>8</position>
</field>
<field>
<name>PWM_EN</name>
<position>7</position>
</field>
<field>
<name>PWM_IN_EN</name>
<position>6</position>
</field>
<field>
<name>PRESCALE</name>
<position>3</position>
<width>3</width>
<enum>
<name>1</name>
<value>0x0</value>
</enum>
<enum>
<name>4</name>
<value>0x1</value>
</enum>
<enum>
<name>16</name>
<value>0x2</value>
</enum>
<enum>
<name>64</name>
<value>0x3</value>
</enum>
<enum>
<name>256</name>
<value>0x4</value>
</enum>
<enum>
<name>1024</name>
<value>0x5</value>
</enum>
</field>
<field>
<name>EXT_EN</name>
<position>2</position>
</field>
<field>
<name>RTC_EN</name>
<position>1</position>
</field>
<field>
<name>PCK_EN</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>STATUS</name>
<title>Timer status register</title>
<instance>
<name>TSTR</name>
<address>0xf0</address>
</instance>
<register>
<field>
<name>REAL2</name>
<position>18</position>
</field>
<field>
<name>REAL1</name>
<position>17</position>
</field>
<field>
<name>BUSY2</name>
<position>2</position>
</field>
<field>
<name>BUSY1</name>
<position>1</position>
</field>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
</node>
<node>
<name>WDT</name>
<title>Watchdog timer module</title>
<instance>
<name>WDT</name>
<address>0xb0002000</address>
</instance>
<node>
<name>DATA</name>
<instance>
<name>DATA</name>
<address>0x0</address>
</instance>
<register>
<width>16</width>
</register>
</node>
<node>
<name>ENABLE</name>
<title>Watchdog counter enable register</title>
<instance>
<name>ENABLE</name>
<address>0x4</address>
</instance>
<register>
<width>8</width>
<field>
<name>TCEN</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>COUNT</name>
<instance>
<name>COUNT</name>
<address>0x8</address>
</instance>
<register>
<width>16</width>
</register>
</node>
<node>
<name>CTRL</name>
<title>Watchdog control register</title>
<instance>
<name>CTRL</name>
<address>0xc</address>
</instance>
<register>
<width>16</width>
<field>
<name>PRESCALE</name>
<position>3</position>
<width>3</width>
<enum>
<name>1</name>
<value>0x0</value>
</enum>
<enum>
<name>4</name>
<value>0x1</value>
</enum>
<enum>
<name>16</name>
<value>0x2</value>
</enum>
<enum>
<name>64</name>
<value>0x3</value>
</enum>
<enum>
<name>256</name>
<value>0x4</value>
</enum>
<enum>
<name>1024</name>
<value>0x5</value>
</enum>
</field>
<field>
<name>CLKIN</name>
<position>0</position>
<width>3</width>
<enum>
<name>PCK</name>
<value>0x1</value>
</enum>
<enum>
<name>RTC</name>
<value>0x2</value>
</enum>
<enum>
<name>EXT</name>
<value>0x4</value>
</enum>
</field>
</register>
</node>
</node>
<node>
<name>RTC</name>
<title>Real time clock module(RTC) address definition</title>
<instance>
<name>RTC</name>
<address>0xb0003000</address>
</instance>
<node>
<name>RTCCR</name>
<title>RTC control register</title>
<instance>
<name>RTCCR</name>
<address>0x0</address>
</instance>
<register>
<field>
<name>WRDY</name>
<position>7</position>
</field>
<field>
<name>1HZ</name>
<position>6</position>
</field>
<field>
<name>1HZIE</name>
<position>5</position>
</field>
<field>
<name>AF</name>
<position>4</position>
</field>
<field>
<name>AIE</name>
<position>3</position>
</field>
<field>
<name>AE</name>
<position>2</position>
</field>
<field>
<name>SELEXC</name>
<position>1</position>
</field>
<field>
<name>RTCE</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>RTCSR</name>
<instance>
<name>RTCSR</name>
<address>0x4</address>
</instance>
<register/>
</node>
<node>
<name>RTCSAR</name>
<instance>
<name>RTCSAR</name>
<address>0x8</address>
</instance>
<register/>
</node>
<node>
<name>RTCGR</name>
<title>RTC regulator register</title>
<instance>
<name>RTCGR</name>
<address>0xc</address>
</instance>
<register>
<field>
<name>LOCK</name>
<position>31</position>
</field>
<field>
<name>ADJC</name>
<position>16</position>
<width>10</width>
</field>
<field>
<name>NC1HZ</name>
<position>0</position>
<width>16</width>
</field>
</register>
</node>
<node>
<name>HCR</name>
<title>Hibernate control register</title>
<instance>
<name>HCR</name>
<address>0x20</address>
</instance>
<register>
<field>
<name>PD</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>HWFCR</name>
<title>Hibernate wakeup filter counter register</title>
<instance>
<name>HWFCR</name>
<address>0x24</address>
</instance>
<register>
<field>
<name>HWFCR</name>
<position>5</position>
<width>11</width>
</field>
</register>
</node>
<node>
<name>HRCR</name>
<title>Hibernate reset counter register</title>
<instance>
<name>HRCR</name>
<address>0x28</address>
</instance>
<register>
<field>
<name>HRCR</name>
<position>5</position>
<width>7</width>
</field>
</register>
</node>
<node>
<name>HWCR</name>
<title>Hibernate wakeup control register</title>
<instance>
<name>HWCR</name>
<address>0x2c</address>
</instance>
<register>
<field>
<name>EPDET</name>
<position>3</position>
</field>
<field>
<name>WKUPVL</name>
<position>2</position>
</field>
<field>
<name>EALM</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>HWRSR</name>
<title>Hibernate wakeup status register</title>
<instance>
<name>HWRSR</name>
<address>0x30</address>
</instance>
<register>
<field>
<name>APD</name>
<position>8</position>
</field>
<field>
<name>HR</name>
<position>5</position>
</field>
<field>
<name>PPR</name>
<position>4</position>
</field>
<field>
<name>PIN</name>
<position>1</position>
</field>
<field>
<name>ALM</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>HSPR</name>
<title>Hibernate scratch pattern register</title>
<instance>
<name>HSPR</name>
<address>0x34</address>
</instance>
<register/>
</node>
<node>
<name>WENR</name>
<title>write enable pattern register</title>
<instance>
<name>WENR</name>
<address>0x3c</address>
</instance>
<register>
<field>
<name>WEN</name>
<position>31</position>
</field>
<field>
<name>WENPAT</name>
<position>0</position>
<width>16</width>
</field>
</register>
</node>
</node>
<node>
<name>GPIO</name>
<title>General purpose I/O port module(GPIO) address definition</title>
<instance>
<name>GPIO</name>
<address>0xb0010000</address>
</instance>
<node>
<name>IN</name>
<title>Port IN</title>
<instance>
<name>IN</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0x00</formula>
</range>
</instance>
<register/>
</node>
<node>
<name>OUT</name>
<title>Port OUT</title>
<instance>
<name>OUT</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0x10</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>FLGC</name>
<instance>
<name>FLGC</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0x14</formula>
</range>
</instance>
<register/>
</node>
<node>
<name>MASK</name>
<instance>
<name>MASK</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0x20</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>PULL</name>
<instance>
<name>PULL</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0x30</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>FUN</name>
<title>Function</title>
<instance>
<name>FUN</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0x40</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>SEL</name>
<title>Select</title>
<instance>
<name>SEL</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0x50</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>DIR</name>
<title>Direction</title>
<instance>
<name>DIR</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0x60</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>TRG</name>
<title>Trigger</title>
<instance>
<name>TRG</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0x70</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>FLG</name>
<title>Flag</title>
<instance>
<name>FLG</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0x80</formula>
</range>
</instance>
<register/>
</node>
<node>
<name>DRIVE0</name>
<title>Drive strength 0</title>
<instance>
<name>DRIVE0</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0xc0</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>DRIVE1</name>
<instance>
<name>DRIVE1</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0xd0</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>DRIVE2</name>
<instance>
<name>DRIVE2</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0xe0</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
<node>
<name>SLEW</name>
<title>Slew rate control</title>
<instance>
<name>SLEW</name>
<range>
<first>0</first>
<count>6</count>
<formula variable="n">(n)*0x100 + 0xf0</formula>
</range>
</instance>
<register>
<variant>
<type>set</type>
<offset>4</offset>
</variant>
<variant>
<type>clr</type>
<offset>8</offset>
</variant>
</register>
</node>
</node>
<node>
<name>AIC</name>
<title>AC97 and I2S controller module</title>
<instance>
<name>AIC</name>
<address>0xb0020000</address>
</instance>
<node>
<name>FR</name>
<title>AIC controller configuration register</title>
<instance>
<name>FR</name>
<address>0x0</address>
</instance>
<register>
<field>
<name>RFTH</name>
<position>24</position>
<width>4</width>
</field>
<field>
<name>TFTH</name>
<position>16</position>
<width>5</width>
</field>
<field>
<name>LSMP</name>
<position>6</position>
</field>
<field>
<name>ICDC</name>
<position>5</position>
</field>
<field>
<name>AUSEL</name>
<position>4</position>
</field>
<field>
<name>RST</name>
<position>3</position>
</field>
<field>
<name>BCKD</name>
<position>2</position>
</field>
<field>
<name>SYNCD</name>
<position>1</position>
</field>
<field>
<name>ENB</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>CR</name>
<title>AIC controller common control register</title>
<instance>
<name>CR</name>
<address>0x4</address>
</instance>
<register>
<field>
<name>PACK16</name>
<position>28</position>
</field>
<field>
<name>CHANNEL</name>
<position>24</position>
<width>3</width>
</field>
<field>
<name>OSS</name>
<position>19</position>
<width>3</width>
</field>
<field>
<name>ISS</name>
<position>16</position>
<width>3</width>
</field>
<field>
<name>RDMS</name>
<position>15</position>
</field>
<field>
<name>TDMS</name>
<position>14</position>
</field>
<field>
<name>M2S</name>
<position>11</position>
</field>
<field>
<name>ENDSW</name>
<position>10</position>
</field>
<field>
<name>AVSTSU</name>
<position>9</position>
</field>
<field>
<name>TFLUSH</name>
<position>8</position>
</field>
<field>
<name>RFLUSH</name>
<position>7</position>
</field>
<field>
<name>EROR</name>
<position>6</position>
</field>
<field>
<name>ETUR</name>
<position>5</position>
</field>
<field>
<name>ERFS</name>
<position>4</position>
</field>
<field>
<name>ETFS</name>
<position>3</position>
</field>
<field>
<name>ENLBF</name>
<position>2</position>
</field>
<field>
<name>ERPL</name>
<position>1</position>
</field>
<field>
<name>EREC</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>ACCR1</name>
<title>AIC controller AC-link control register 1</title>
<instance>
<name>ACCR1</name>
<address>0x8</address>
</instance>
<register>
<field>
<name>RS</name>
<position>16</position>
<width>10</width>
</field>
<field>
<name>XS</name>
<position>0</position>
<width>10</width>
</field>
</register>
</node>
<node>
<name>ACCR2</name>
<title>AIC controller AC-link control register 2</title>
<instance>
<name>ACCR2</name>
<address>0xc</address>
</instance>
<register>
<field>
<name>ERSTO</name>
<position>18</position>
</field>
<field>
<name>ESADR</name>
<position>17</position>
</field>
<field>
<name>ECADT</name>
<position>16</position>
</field>
<field>
<name>SO</name>
<position>3</position>
</field>
<field>
<name>SR</name>
<position>2</position>
</field>
<field>
<name>SS</name>
<position>1</position>
</field>
<field>
<name>SA</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>I2SCR</name>
<title>AIC controller i2s/msb-justified control register</title>
<instance>
<name>I2SCR</name>
<address>0x10</address>
</instance>
<register>
<field>
<name>RFIRST</name>
<position>17</position>
</field>
<field>
<name>SWLH</name>
<position>16</position>
</field>
<field>
<name>STPBK</name>
<position>12</position>
</field>
<field>
<name>ESCLK</name>
<position>4</position>
</field>
<field>
<name>AMSL</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>SR</name>
<title>AIC controller FIFO status register</title>
<instance>
<name>SR</name>
<address>0x14</address>
</instance>
<register>
<field>
<name>RFL</name>
<position>24</position>
<width>6</width>
</field>
<field>
<name>TFL</name>
<position>8</position>
<width>6</width>
</field>
<field>
<name>ROR</name>
<position>6</position>
</field>
<field>
<name>TUR</name>
<position>5</position>
</field>
<field>
<name>RFS</name>
<position>4</position>
</field>
<field>
<name>TFS</name>
<position>3</position>
</field>
</register>
</node>
<node>
<name>ACSR</name>
<title>AIC controller AC-link status register</title>
<instance>
<name>ACSR</name>
<address>0x18</address>
</instance>
<register>
<field>
<name>SLTERR</name>
<position>21</position>
</field>
<field>
<name>CRDY</name>
<position>20</position>
</field>
<field>
<name>CLPM</name>
<position>19</position>
</field>
<field>
<name>RSTO</name>
<position>18</position>
</field>
<field>
<name>SADR</name>
<position>17</position>
</field>
<field>
<name>CADT</name>
<position>16</position>
</field>
</register>
</node>
<node>
<name>I2SSR</name>
<title>AIC controller I2S/MSB-justified status register</title>
<instance>
<name>I2SSR</name>
<address>0x1c</address>
</instance>
<register>
<field>
<name>CHBSY</name>
<position>5</position>
</field>
<field>
<name>TBSY</name>
<position>4</position>
</field>
<field>
<name>RBSY</name>
<position>3</position>
</field>
<field>
<name>BSY</name>
<position>2</position>
</field>
</register>
</node>
<node>
<name>ACCAR</name>
<title>AIC controller AC97 codec command address register</title>
<instance>
<name>ACCAR</name>
<address>0x20</address>
</instance>
<register>
<field>
<name>CAR</name>
<position>0</position>
<width>20</width>
</field>
</register>
</node>
<node>
<name>ACCDR</name>
<title>AIC controller AC97 codec command data register</title>
<instance>
<name>ACCDR</name>
<address>0x24</address>
</instance>
<register>
<field>
<name>CDR</name>
<position>0</position>
<width>20</width>
</field>
</register>
</node>
<node>
<name>ACSAR</name>
<title>AIC controller AC97 codec status address register</title>
<instance>
<name>ACSAR</name>
<address>0x28</address>
</instance>
<register>
<field>
<name>SAR</name>
<position>0</position>
<width>20</width>
</field>
</register>
</node>
<node>
<name>ACSDR</name>
<title>AIC controller AC97 codec status data register</title>
<instance>
<name>ACSDR</name>
<address>0x2c</address>
</instance>
<register>
<field>
<name>SDR</name>
<position>0</position>
<width>20</width>
</field>
</register>
</node>
<node>
<name>I2SDIV</name>
<title>AIC controller I2S/MSB-justified clock divider register</title>
<instance>
<name>I2SDIV</name>
<address>0x30</address>
</instance>
<register>
<field>
<name>DIV</name>
<position>0</position>
<width>4</width>
</field>
</register>
</node>
<node>
<name>DR</name>
<instance>
<name>DR</name>
<address>0x34</address>
</instance>
<register/>
</node>
<node>
<name>SPENA</name>
<title>SPDIF enable register</title>
<instance>
<name>SPENA</name>
<address>0x80</address>
</instance>
<register>
<field>
<name>SPEN</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>SPCTRL</name>
<title>SPDIF control register</title>
<instance>
<name>SPCTRL</name>
<address>0x84</address>
</instance>
<register>
<field>
<name>DMAEN</name>
<position>15</position>
</field>
<field>
<name>DTYPE</name>
<position>14</position>
</field>
<field>
<name>SIGN</name>
<position>13</position>
</field>
<field>
<name>INVALID</name>
<position>12</position>
</field>
<field>
<name>RST</name>
<position>11</position>
</field>
<field>
<name>SPDIFI2S</name>
<position>10</position>
</field>
<field>
<name>MTRIG</name>
<position>1</position>
</field>
<field>
<name>MFFUR</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>SPSTATE</name>
<title>SPDIF state register</title>
<instance>
<name>SPSTATE</name>
<address>0x88</address>
</instance>
<register>
<field>
<name>FLVL</name>
<position>8</position>
<width>7</width>
</field>
<field>
<name>BUSY</name>
<position>7</position>
</field>
<field>
<name>FTRIG</name>
<position>1</position>
</field>
<field>
<name>FUR</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>SPCFG1</name>
<title>SPDIF configure 1 register</title>
<instance>
<name>SPCFG1</name>
<address>0x8c</address>
</instance>
<register>
<field>
<name>INITLVL</name>
<position>17</position>
</field>
<field>
<name>ZROVLD</name>
<position>16</position>
</field>
<field>
<name>TRIG</name>
<position>12</position>
<width>2</width>
</field>
<field>
<name>SRCNUM</name>
<position>8</position>
<width>4</width>
</field>
<field>
<name>CH1NUM</name>
<position>4</position>
<width>4</width>
</field>
<field>
<name>CH2NUM</name>
<position>0</position>
<width>4</width>
</field>
</register>
</node>
<node>
<name>SPCFG2</name>
<title>SPDIF configure 2 register</title>
<instance>
<name>SPCFG2</name>
<address>0x90</address>
</instance>
<register>
<field>
<name>FS</name>
<position>26</position>
<width>4</width>
</field>
<field>
<name>ORGFRQ</name>
<position>22</position>
<width>4</width>
</field>
<field>
<name>SAMWL</name>
<position>19</position>
<width>3</width>
</field>
<field>
<name>MAXWL</name>
<position>18</position>
</field>
<field>
<name>CLKACU</name>
<position>16</position>
<width>2</width>
</field>
<field>
<name>CATCODE</name>
<position>8</position>
<width>8</width>
</field>
<field>
<name>CHMD</name>
<position>6</position>
<width>2</width>
</field>
<field>
<name>PRE</name>
<position>3</position>
</field>
<field>
<name>COPYN</name>
<position>2</position>
</field>
<field>
<name>AUDION</name>
<position>1</position>
</field>
<field>
<name>CONPRO</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>SPFIFO</name>
<instance>
<name>SPFIFO</name>
<address>0x94</address>
</instance>
<register/>
</node>
<node>
<name>RGADW</name>
<title>ICDC internal register access control register</title>
<instance>
<name>RGADW</name>
<address>0xa4</address>
</instance>
<register>
<field>
<name>RGWR</name>
<position>16</position>
</field>
<field>
<name>RGADDR</name>
<position>8</position>
<width>7</width>
</field>
<field>
<name>RGDIN</name>
<position>0</position>
<width>8</width>
</field>
</register>
</node>
<node>
<name>RGDATA</name>
<title>ICDC internal register data output register</title>
<instance>
<name>RGDATA</name>
<address>0xa8</address>
</instance>
<register>
<field>
<name>IRQ</name>
<position>8</position>
</field>
<field>
<name>RGDOUT</name>
<position>0</position>
<width>8</width>
</field>
</register>
</node>
</node>
<node>
<name>MSC</name>
<instance>
<name>MSC</name>
<range>
<first>0</first>
<address>0xb0021000</address>
<address>0xb0022000</address>
<address>0xb0023000</address>
</range>
</instance>
<node>
<name>STRPCL</name>
<title>MSC Clock and Control Register</title>
<instance>
<name>STRPCL</name>
<address>0x0</address>
</instance>
<register>
<width>16</width>
<field>
<name>SEND_CCSD</name>
<desc>send command completion signal disable to ceata</desc>
<position>15</position>
</field>
<field>
<name>SEND_AS_CCSD</name>
<desc>send internally generated stop after sending ccsd</desc>
<position>14</position>
</field>
<field>
<name>EXIT_MULTIPLE</name>
<position>7</position>
</field>
<field>
<name>EXIT_TRANSFER</name>
<position>6</position>
</field>
<field>
<name>START_READWAIT</name>
<position>5</position>
</field>
<field>
<name>STOP_READWAIT</name>
<position>4</position>
</field>
<field>
<name>RESET</name>
<position>3</position>
</field>
<field>
<name>START_OP</name>
<position>2</position>
</field>
<field>
<name>CLOCK_CONTROL</name>
<desc>Start MMC/SD clock</desc>
<position>0</position>
<width>2</width>
<enum>
<name>STOP</name>
<value>0x1</value>
</enum>
<enum>
<name>START</name>
<value>0x2</value>
</enum>
</field>
</register>
</node>
<node>
<name>STAT</name>
<title>MSC Status Register</title>
<instance>
<name>STAT</name>
<address>0x4</address>
</instance>
<register>
<field>
<name>AUTO_CMD_DONE</name>
<desc>12 is internally generated by controller has finished</desc>
<position>31</position>
</field>
<field>
<name>IS_RESETTING</name>
<position>15</position>
</field>
<field>
<name>SDIO_INT_ACTIVE</name>
<position>14</position>
</field>
<field>
<name>PRG_DONE</name>
<position>13</position>
</field>
<field>
<name>DATA_TRAN_DONE</name>
<position>12</position>
</field>
<field>
<name>END_CMD_RES</name>
<position>11</position>
</field>
<field>
<name>DATA_FIFO_AFULL</name>
<position>10</position>
</field>
<field>
<name>IS_READWAIT</name>
<position>9</position>
</field>
<field>
<name>CLK_EN</name>
<position>8</position>
</field>
<field>
<name>DATA_FIFO_FULL</name>
<position>7</position>
</field>
<field>
<name>DATA_FIFO_EMPTY</name>
<position>6</position>
</field>
<field>
<name>CRC_RES_ERR</name>
<position>5</position>
</field>
<field>
<name>CRC_READ_ERROR</name>
<position>4</position>
</field>
<field>
<name>CRC_WRITE_ERROR</name>
<desc>No CRC status is sent back</desc>
<position>2</position>
<width>2</width>
<enum>
<name>NO</name>
<value>0x0</value>
</enum>
<enum>
<name>DATA</name>
<value>0x1</value>
</enum>
<enum>
<name>NOSTS</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>TIME_OUT_RES</name>
<position>1</position>
</field>
<field>
<name>TIME_OUT_READ</name>
<position>0</position>
</field>
</register>
</node>
<node>
<name>CLKRT</name>
<title>MSC Bus Clock Control Register</title>
<instance>
<name>CLKRT</name>
<address>0x8</address>
</instance>
<register>
<width>16</width>
<field>
<name>CLK_RATE</name>
<desc>1/128 of CLK_SRC</desc>
<position>0</position>
<width>3</width>
<enum>
<name>DIV_1</name>
<value>0x0</value>
</enum>
<enum>
<name>DIV_2</name>
<value>0x1</value>
</enum>
<enum>
<name>DIV_4</name>
<value>0x2</value>
</enum>
<enum>
<name>DIV_8</name>
<value>0x3</value>
</enum>
<enum>
<name>DIV_16</name>
<value>0x4</value>
</enum>
<enum>
<name>DIV_32</name>
<value>0x5</value>
</enum>
<enum>
<name>DIV_64</name>
<value>0x6</value>
</enum>
<enum>
<name>DIV_128</name>
<value>0x7</value>
</enum>
</field>
</register>
</node>
<node>
<name>CMDAT</name>
<title>MSC Command Sequence Control Register</title>
<instance>
<name>CMDAT</name>
<address>0xc</address>
</instance>
<register>
<field>
<name>CCS_EXPECTED</name>
<desc>interrupts are enabled in ce-ata</desc>
<position>31</position>
</field>
<field>
<name>READ_CEATA</name>
<position>30</position>
</field>
<field>
<name>SDIO_PRDT</name>
<desc>exact 2 cycle</desc>
<position>17</position>
</field>
<field>
<name>SEND_AS_STOP</name>
<position>16</position>
</field>
<field>
<name>RTRG</name>
<desc>reset value</desc>
<position>14</position>
<width>2</width>
<enum>
<name>EQUALT_8</name>
<value>0x0</value>
</enum>
<enum>
<name>EQUALT_16</name>
<value>0x1</value>
</enum>
<enum>
<name>EQUALT_24</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>TTRG</name>
<desc>reset value</desc>
<position>12</position>
<width>2</width>
<enum>
<name>LESS_8</name>
<value>0x0</value>
</enum>
<enum>
<name>LESS_16</name>
<value>0x1</value>
</enum>
<enum>
<name>LESS_24</name>
<value>0x2</value>
</enum>
</field>
<field>
<name>STOP_ABORT</name>
<position>11</position>
</field>
<field>
<name>BUS_WIDTH</name>
<desc>8-bit data bus</desc>
<position>9</position>
<width>2</width>
<enum>
<name>1BIT</name>
<value>0x0</value>
</enum>
<enum>
<name>4BIT</name>
<value>0x2</value>
</enum>
<enum>
<name>8BIT</name>
<value>0x3</value>
</enum>
</field>
<field>
<name>DMA_EN</name>
<position>8</position>
</field>
<field>
<name>INIT</name>
<position>7</position>
</field>
<field>
<name>BUSY</name>
<position>6</position>
</field>
<field>
<name>STREAM_BLOCK</name>
<position>5</position>
</field>
<field>
<name>WRITE</name>
<position>4</position>
</field>
<field>
<name>DATA_EN</name>
<position>3</position>
</field>
<field>
<name>RESPONSE</name>
<desc>Format R6</desc>
<position>0</position>
<width>3</width>
<enum>
<name>NONE</name>
<value>0x0</value>
</enum>
<enum>
<name>R1</name>
<value>0x1</value>
</enum>
<enum>
<name>R2</name>
<value>0x2</value>
</enum>
<enum>
<name>R3</name>
<value>0x3</value>
</enum>
<enum>
<name>R4</name>
<value>0x4</value>
</enum>
<enum>
<name>R5</name>
<value>0x5</value>
</enum>
<enum>
<name>R6</name>
<value>0x6</value>
</enum>
</field>
</register>
</node>
<node>
<name>RESTO</name>
<instance>
<name>RESTO</name>
<address>0x10</address>
</instance>
<register>
<width>16</width>
</register>
</node>
<node>
<name>RDTO</name>
<instance>
<name>RDTO</name>
<address>0x14</address>
</instance>
<register/>
</node>
<node>
<name>BLKLEN</name>
<instance>
<name>BLKLEN</name>
<address>0x18</address>
</instance>
<register>
<width>16</width>
</register>
</node>
<node>
<name>NOB</name>
<instance>
<name>NOB</name>
<address>0x1c</address>
</instance>
<register>
<width>16</width>
</register>
</node>
<node>
<name>SNOB</name>
<instance>
<name>SNOB</name>
<address>0x20</address>
</instance>
<register>
<width>16</width>
</register>
</node>
<node>
<name>IMASK</name>
<title>MSC Interrupts Mask Register</title>
<instance>
<name>IMASK</name>
<address>0x24</address>
</instance>
<register>
<field>
<name>AUTO_CMD_DONE</name>
<position>15</position>
</field>
<field>
<name>DATA_FIFO_FULL</name>
<position>14</position>
</field>
<field>
<name>DATA_FIFO_EMP</name>
<position>