commit 4829f7835a9f1965263438f2ee9587dc19408397
author Michael Sevakis <jethead71@rockbox.org> Wed Oct 17 00:01:03 2007 +0000
committer Michael Sevakis <jethead71@rockbox.org> Wed Oct 17 00:01:03 2007 +0000
tree 1a6945c53234c78790d95ad3ecd75393bde3b0b4
parent fc43b9df823af80dd1c9cf7dc1b5de6703944043

Apply Akio Idehara's fix for FS#7972 - Fix ARM's swp (xchg) inline assembly for gcc 4.2. Also avoids UNPREDICTABLE behavior that GCC should have always warned about.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15157 a1c6a512-1295-4272-9138-f99709370657

firmware/export/thread.h

diff --git a/firmware/export/thread.h b/firmware/export/thread.h
index 89eb651..867c587 100644
--- a/firmware/export/thread.h
+++ b/firmware/export/thread.h
@@ -372,7 +372,7 @@
 ({  uint32_t o;                \
     asm volatile(              \
         "swpb %0, %1, [%2]"    \
-        : "=r"(o)              \
+        : "=&r"(o)             \
         : "r"(v),              \
           "r"((uint8_t*)(a))); \
     o; })
@@ -381,7 +381,7 @@
 ({  uint32_t o;                 \
     asm volatile(               \
         "swp %0, %1, [%2]"      \
-        : "=r"(o)               \
+        : "=&r"(o)              \
         : "r"((uint32_t)(v)),   \
           "r"((uint32_t*)(a))); \
     o; })
@@ -390,7 +390,7 @@
 ({  typeof (*(a)) o;        \
     asm volatile(           \
         "swp %0, %1, [%2]"  \
-        : "=r"(o)           \
+        : "=&r"(o)          \
         : "r"(v), "r"(a));  \
     o; })
 #endif /* locking selection */