Seperate M:Robe crt0.S, fix the vector tables for the bootloader, and show touchscreen values on single line.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14814 a1c6a512-1295-4272-9138-f99709370657
diff --git a/bootloader/mrobe500.c b/bootloader/mrobe500.c
index 50c2acb..1bfadd4 100755
--- a/bootloader/mrobe500.c
+++ b/bootloader/mrobe500.c
@@ -41,13 +41,15 @@
 #include "spi-target.h"

 #include "uart-target.h"

 

+extern int line;

+

 void main(void)

 {

-    unsigned char* loadbuffer;

+/*    unsigned char* loadbuffer;

     int buffer_size;

     int rc;

     int(*kernel_entry)(void);

-

+*/

     power_init();

     system_init();

     kernel_init();

@@ -115,12 +117,14 @@
         unsigned char out[] = {command >> 8, command & 0xff};

         unsigned char in[8];

         dm320_spi_block_transfer(out, sizeof(out), in, sizeof(in));

-        

+

         printf("%02x%02x %02x%02x %02x%02x %02x%02x\n",

             in[0], in[1],

             in[2], in[3],

             in[4], in[5],

             in[6], in[7]);

+        line--;

+

     }

 #if 0

     rc = ata_init();

diff --git a/firmware/SOURCES b/firmware/SOURCES
index 9dd617b..454f9e1 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -327,6 +327,8 @@
 #endif
 #elif CONFIG_CPU == PNX0101
 target/arm/pnx0101/crt0-pnx0101.S
+#elif defined(OLYMPUS_MROBE_500)
+target/arm/olympus/mrobe-500/crt0.S
 #elif defined(CPU_ARM)
 target/arm/crt0.S
 #endif /* defined(CPU_*) */
@@ -790,7 +792,7 @@
 target/arm/pnx0101/iriver-ifp7xx/lcd-ifp7xx.c
 target/arm/pnx0101/iriver-ifp7xx/power-ifp7xx.c
 target/arm/pnx0101/iriver-ifp7xx/powermgmt-ifp7xx.c
-target/arm/pnx0101/iriver-ifp7xx/usb-ifp7xx.c
+target/arm/pnx0101/iriver-ifp7xx/usb-ifp7xx.c   
 #ifndef BOOTLOADER
 target/arm/pnx0101/pcm-pnx0101.c
 #endif
diff --git a/firmware/boot.lds b/firmware/boot.lds
index 999e1b0..e3dbb49 100644
--- a/firmware/boot.lds
+++ b/firmware/boot.lds
@@ -9,6 +9,8 @@
 OUTPUT_ARCH(arm)
 #ifdef CPU_PP
 INPUT(target/arm/crt0-pp-bl.o)
+#elif defined(OLYMPUS_MROBE_500)
+INPUT(target/arm/olympus/mrobe-500/crt0.o)
 #else
 INPUT(target/arm/crt0.o)
 #endif
@@ -169,14 +171,6 @@
 {
     . = DRAMORIG + 0x1000000;
 
-    .vectors 0x0 :
-    {
-        _vectorsstart = .;
-        *(.vectors);
-        _vectorsend = .;
-    } AT> DRAM
-    _vectorscopy = LOADADDR(.vectors);
-
     .text : {
         *(.init.text)
         *(.text*)
@@ -215,12 +209,26 @@
          _stackend = .;
          stackend = .;
     } >DRAM
+
     .bss : {
          _edata = .;
          *(.bss*);
          *(.ibss);
          _end = .;
      }>DRAM
+     
+    .vectors 0x0 :
+    {
+        loadaddress = .;
+        _loadaddress = .;
+        _vectorsstart = .;
+        KEEP(*(.resetvectors));
+        *(.resetvectors);
+        KEEP(*(.vectors));
+        *(.vectors);
+        _vectorsend = .;
+    } AT> DRAM
+    _vectorscopy = LOADADDR(.vectors);
 }
 #elif (CONFIG_CPU==IMX31L)
 {
diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S
index d734f82..c01a4fe 100644
--- a/firmware/target/arm/crt0.S
+++ b/firmware/target/arm/crt0.S
@@ -428,36 +428,11 @@
     .space 256*4
 fiq_stack:
 
-#else
-    /* get the high part of our execute address */
-    ldr    r2, =0xffffff00
-    and    r4, pc, r2
-    
-    /* Copy bootloader to safe area - 0x01900000 */
-    mov    r5, #0x00900000
-    add    r5, r5, #0x01000000
-    ldr    r6, = _dataend
-    sub    r0, r6, r5       /* length of loader */
-    add    r0, r4, r0     /* r0 points to start of loader */
-1:
-    cmp    r5, r6
-    ldrcc  r2, [r4], #4
-    strcc  r2, [r5], #4
-    bcc    1b
-
-    ldr    pc, =start_loc    /* jump to the relocated start_loc:  */
-    
-start_loc:
-     bl main
-
 #endif
 
 #else /* BOOTLOADER */
-    
 
-
-
-	 /* Set up stack for IRQ mode */ 
+	 /* Set up stack for IRQ mode */
     msr    cpsr_c, #0xd2
     ldr    sp, =irq_stack
     /* Set up stack for FIQ mode */ 
@@ -549,4 +524,4 @@
     .space 256*4
 fiq_stack:
 
-#endif /* BOOTLOADER */ 
+#endif /* BOOTLOADER */
diff --git a/firmware/target/arm/olympus/mrobe-500/adc-mr500.c b/firmware/target/arm/olympus/mrobe-500/adc-mr500.c
index 4fb2aa3..39d92d6 100644
--- a/firmware/target/arm/olympus/mrobe-500/adc-mr500.c
+++ b/firmware/target/arm/olympus/mrobe-500/adc-mr500.c
@@ -5,7 +5,7 @@
  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
- * $Id: $
+ * $Id$
  *
  * Copyright (C) 2007 by Karl Kurbjun
  *
diff --git a/firmware/target/arm/olympus/mrobe-500/crt0.S b/firmware/target/arm/olympus/mrobe-500/crt0.S
new file mode 100755
index 0000000..cf6d02a
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/crt0.S
@@ -0,0 +1,196 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2002 by Linus Nielsen Feltzing
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "cpu.h"
+
+    .section .init.text,"ax",%progbits
+
+    .global    start
+start:
+    msr    cpsr, #0xd3 /* enter supervisor mode, disable IRQ */
+
+#if !defined(DEBUG)
+    /* Copy exception handler code to address 0 */
+    ldr    r2, =_vectorsstart
+    ldr    r3, =_vectorsend
+    ldr    r4, =_vectorscopy
+1:
+    cmp    r3, r2
+    ldrhi  r5, [r4], #4
+    strhi  r5, [r2], #4
+    bhi    1b
+#else
+    ldr    r1, =vectors
+    ldr    r0, =irq_handler
+    str    r0, [r1, #24]
+    ldr    r0, =fiq_handler
+    str    r0, [r1, #28]
+#endif
+
+#if !defined(BOOTLOADER)
+
+#if !defined(STUB)
+    /* Zero out IBSS */
+    ldr    r2, =_iedata
+    ldr    r3, =_iend
+    mov    r4, #0
+1:
+    cmp    r3, r2
+    strhi  r4, [r2], #4
+    bhi    1b
+
+    /* Copy the IRAM */
+    ldr    r2, =_iramcopy
+    ldr    r3, =_iramstart
+    ldr    r4, =_iramend
+1:
+    cmp    r4, r3
+    ldrhi  r5, [r2], #4
+    strhi  r5, [r3], #4
+    bhi    1b
+#endif /* !STUB */
+#endif /* !BOOTLOADER */
+
+    /* Initialise bss section to zero */
+    ldr    r2, =_edata
+    ldr    r3, =_end
+    mov    r4, #0
+1:
+    cmp    r3, r2
+    strhi  r4, [r2], #4
+    bhi    1b
+    
+    /* Set up some stack and munge it with 0xdeadbeef */
+    ldr    r3, =stackend
+    ldr    r2, =stackbegin
+    ldr    r4, =0xdeadbeef
+1:
+    cmp    r3, r2
+    strhi  r4, [r2], #4
+    bhi    1b
+
+	 /* Set up stack for IRQ mode */
+    msr    cpsr_c, #0xd2
+    ldr    sp, =irq_stack
+    /* Set up stack for FIQ mode */
+    msr    cpsr_c, #0xd1
+    ldr    sp, =fiq_stack
+
+    /* Let abort and undefined modes use IRQ stack */
+    msr    cpsr_c, #0xd7
+    ldr    sp, =irq_stack
+    msr    cpsr_c, #0xdb
+    ldr    sp, =irq_stack
+    /* Switch to supervisor mode */
+    msr    cpsr_c, #0xd3
+    ldr    sp, =stackend
+
+#ifdef BOOTLOADER
+    /* get the high part of our execute address */
+    ldr    r2, =0xffffff00
+    and    r4, pc, r2
+
+    /* Copy bootloader to safe area - 0x01900000 */
+    mov    r5, #0x00900000
+    add    r5, r5, #0x01000000
+    ldr    r6, = _dataend
+    sub    r0, r6, r5       /* length of loader */
+    add    r0, r4, r0     /* r0 points to start of loader */
+1:
+    cmp    r5, r6
+    ldrcc  r2, [r4], #4
+    strcc  r2, [r5], #4
+    bcc    1b
+
+    ldr    pc, =start_loc    /* jump to the relocated start_loc:  */
+
+#endif
+
+start_loc:
+     bl main
+    /* main() should never return */
+
+/* Exception handlers. Will be copied to address 0 after memory remapping */
+    .section .vectors,"aw"
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+
+    /* Exception vectors */
+    .global vectors
+vectors:
+    .word  start 
+    .word  undef_instr_handler
+    .word  software_int_handler
+    .word  prefetch_abort_handler
+    .word  data_abort_handler
+    .word  reserved_handler
+    .word  irq_handler
+    .word  fiq_handler
+
+    .text
+
+#if !defined(STUB)
+    .global irq
+    .global fiq
+    .global UIE
+#endif
+
+/* All illegal exceptions call into UIE with exception address as first
+   parameter. This is calculated differently depending on which exception
+   we're in. Second parameter is exception number, used for a string lookup
+   in UIE.
+ */
+undef_instr_handler:
+    mov    r0, lr
+    mov    r1, #0
+    b      UIE
+
+/* We run supervisor mode most of the time, and should never see a software
+   exception being thrown. Perhaps make it illegal and call UIE?
+ */
+software_int_handler:
+reserved_handler:
+    movs   pc, lr
+
+prefetch_abort_handler:
+    sub    r0, lr, #4
+    mov    r1, #1
+    b      UIE
+
+data_abort_handler:
+    sub    r0, lr, #8 
+    mov    r1, #2
+    b      UIE
+
+UIE:
+    b UIE
+
+/* 256 words of IRQ stack */
+    .space 256*4
+irq_stack:
+
+/* 256 words of FIQ stack */
+    .space 256*4
+fiq_stack:
diff --git a/firmware/target/arm/olympus/mrobe-500/system-mr500.c b/firmware/target/arm/olympus/mrobe-500/system-mr500.c
index c93c9f6..1163104 100644
--- a/firmware/target/arm/olympus/mrobe-500/system-mr500.c
+++ b/firmware/target/arm/olympus/mrobe-500/system-mr500.c
@@ -5,7 +5,7 @@
  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  *                     \/            \/     \/    \/            \/
- * $Id: $
+ * $Id$
  *
  * Copyright (C) 2007 by Karl Kurbjun
  *
@@ -119,6 +119,26 @@
     );
 }
 
+void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
+void fiq_handler(void)
+{
+    /*
+     * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
+     */
+
+    asm volatile (
+        "sub    lr, lr, #4            \r\n"
+        "stmfd  sp!, {r0-r3, ip, lr}  \r\n"
+        "mov    r0, #0x00030000       \r\n"
+        "ldr    r0, [r0, #0x518]       \r\n"
+        "ldr    r1, =irqvector        \r\n"
+        "ldr    r1, [r1, r0, lsl #2]  \r\n"
+        "mov    lr, pc                \r\n"
+        "bx     r1                    \r\n"
+        "ldmfd  sp!, {r0-r3, ip, pc}^ \r\n"
+    );
+}
+
 void system_reboot(void)
 {