| Michael Sevakis | 0b1d7e7 | 2008-04-11 08:51:27 +0000 | [diff] [blame] | 1 | /*************************************************************************** |
| 2 | * __________ __ ___. |
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
| 7 | * \/ \/ \/ \/ \/ |
| 8 | * $Id$ |
| 9 | * |
| 10 | * Copyright (c) 2008 by Michael Sevakis |
| 11 | * |
| Daniel Stenberg | 2acc0ac | 2008-06-28 18:10:04 +0000 | [diff] [blame^] | 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License |
| 14 | * as published by the Free Software Foundation; either version 2 |
| 15 | * of the License, or (at your option) any later version. |
| Michael Sevakis | 0b1d7e7 | 2008-04-11 08:51:27 +0000 | [diff] [blame] | 16 | * |
| 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
| 18 | * KIND, either express or implied. |
| 19 | * |
| 20 | ****************************************************************************/ |
| 21 | #ifndef _MC13783_H_ |
| 22 | #define _MC13783_H_ |
| 23 | |
| 24 | enum mc13783_regs_enum |
| 25 | { |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 26 | MC13783_INTERRUPT_STATUS0 = 0, |
| 27 | MC13783_INTERRUPT_MASK0 = 1, |
| 28 | MC13783_INTERRUPT_SENSE0 = 2, |
| 29 | MC13783_INTERRUPT_STATUS1 = 3, |
| 30 | MC13783_INTERRUPT_MASK1 = 4, |
| 31 | MC13783_INTERRUPT_SENSE1 = 5, |
| 32 | MC13783_POWER_UP_MODE_SENSE = 6, |
| 33 | MC13783_IDENTIFICATION = 7, |
| 34 | MC13783_SEMAPHORE = 8, |
| 35 | MC13783_ARBITRATION_PERIPHERAL_AUDIO = 9, |
| 36 | MC13783_ARBITRATION_SWITCHERS = 10, |
| 37 | MC13783_ARBITRATION_REGULATORS0 = 11, |
| 38 | MC13783_ARBITRATION_REGULATORS1 = 12, |
| 39 | MC13783_POWER_CONTROL0 = 13, |
| 40 | MC13783_POWER_CONTROL1 = 14, |
| 41 | MC13783_POWER_CONTROL2 = 15, |
| 42 | MC13783_REGEN_ASSIGNMENT = 16, |
| 43 | MC13783_CONTROL_SPARE = 17, /* x */ |
| 44 | MC13783_MEMORYA = 18, |
| 45 | MC13783_MEMORYB = 19, |
| 46 | MC13783_RTC_TIME = 20, |
| 47 | MC13783_RTC_ALARM = 21, |
| 48 | MC13783_RTC_DAY = 22, |
| 49 | MC13783_RTC_DAY_ALARM = 23, |
| 50 | MC13783_SWITCHERS0 = 24, |
| 51 | MC13783_SWITCHERS1 = 25, |
| 52 | MC13783_SWITCHERS2 = 26, |
| 53 | MC13783_SWITCHERS3 = 27, |
| 54 | MC13783_SWITCHERS4 = 28, |
| 55 | MC13783_SWITCHERS5 = 29, |
| 56 | MC13783_REGULATOR_SETTING0 = 30, |
| 57 | MC13783_REGULATOR_SETTING1 = 31, |
| 58 | MC13783_REGULATOR_MODE0 = 32, |
| 59 | MC13783_REGULATOR_MODE1 = 33, |
| 60 | MC13783_POWER_MISCELLANEOUS = 34, |
| 61 | MC13783_POWER_SPARE = 35, /* x */ |
| 62 | MC13783_AUDIO_RX0 = 36, |
| 63 | MC13783_AUDIO_RX1 = 37, |
| 64 | MC13783_AUDIO_TX = 38, |
| 65 | MC13783_SSI_NETWORK = 39, |
| 66 | MC13783_AUDIO_CODEC = 40, |
| 67 | MC13783_AUDIO_STEREO_DAC = 41, |
| 68 | MC13783_AUDIO_SPARE = 42, /* x */ |
| 69 | MC13783_ADC0 = 43, |
| 70 | MC13783_ADC1 = 44, |
| 71 | MC13783_ADC2 = 45, |
| 72 | MC13783_ADC3 = 46, |
| 73 | MC13783_ADC4 = 47, |
| 74 | MC13783_CHARGER = 48, |
| 75 | MC13783_USB0 = 49, |
| 76 | MC13783_CHARGER_USB1 = 50, |
| 77 | MC13783_LED_CONTROL0 = 51, |
| 78 | MC13783_LED_CONTROL1 = 52, |
| 79 | MC13783_LED_CONTROL2 = 53, |
| 80 | MC13783_LED_CONTROL3 = 54, |
| 81 | MC13783_LED_CONTROL4 = 55, |
| 82 | MC13783_LED_CONTROL5 = 56, |
| 83 | MC13783_SPARE = 57, /* x */ |
| 84 | MC13783_TRIM0 = 58, /* x */ |
| 85 | MC13783_TRIM1 = 59, /* x */ |
| 86 | MC13783_TEST0 = 60, /* x */ |
| 87 | MC13783_TEST1 = 61, /* x */ |
| 88 | MC13783_TEST2 = 62, /* x */ |
| 89 | MC13783_TEST3 = 63, /* x */ |
| 90 | MC13783_NUM_REGS = 64, |
| Michael Sevakis | 0b1d7e7 | 2008-04-11 08:51:27 +0000 | [diff] [blame] | 91 | }; |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 92 | /* x = unused/reserved/not implemented */ |
| Michael Sevakis | 0b1d7e7 | 2008-04-11 08:51:27 +0000 | [diff] [blame] | 93 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 94 | /* INTERRUPT_STATUS0 (0) */ |
| 95 | #define MC13783_ADCDONEI (0x1 << 0) |
| 96 | #define MC13783_ADCBISDONEI (0x1 << 1) |
| 97 | #define MC13783_TSI (0x1 << 2) |
| 98 | #define MC13783_WHIGHI (0x1 << 3) |
| 99 | #define MC13783_WLOWI (0x1 << 4) |
| 100 | #define MC13783_CHGDETI (0x1 << 6) |
| 101 | #define MC13783_CHGOVI (0x1 << 7) |
| 102 | #define MC13783_CHGREVI (0x1 << 8) |
| 103 | #define MC13783_CHGSHORTI (0x1 << 9) |
| 104 | #define MC13783_CCCVI (0x1 << 10) |
| 105 | #define MC13783_CHGCURRI (0x1 << 11) |
| 106 | #define MC13783_BPONII (0x1 << 12) |
| 107 | #define MC13783_LOBATLI (0x1 << 13) |
| 108 | #define MC13783_LOBATHI (0x1 << 14) |
| 109 | #define MC13783_UDPI (0x1 << 15) |
| 110 | #define MC13783_USB4V4I (0x1 << 16) |
| 111 | #define MC13783_USB2V0I (0x1 << 17) |
| 112 | #define MC13783_USB0V8I (0x1 << 18) |
| 113 | #define MC13783_IDFLOATI (0x1 << 19) |
| 114 | #define MC13783_SE1I (0x1 << 21) |
| 115 | #define MC13783_CKDETI (0x1 << 22) |
| 116 | #define MC13783_UDMI (0x1 << 23) |
| Nils Wallménius | 8c5d552 | 2008-04-13 10:04:21 +0000 | [diff] [blame] | 117 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 118 | /* INTERRUPT_MASK0 (1) */ |
| 119 | #define MC13783_ADCDONEM (0x1 << 0) |
| 120 | #define MC13783_ADCBISDONEM (0x1 << 1) |
| 121 | #define MC13783_TSM (0x1 << 2) |
| 122 | #define MC13783_WHIGHM (0x1 << 3) |
| 123 | #define MC13783_WLOWM (0x1 << 4) |
| 124 | #define MC13783_CHGDETM (0x1 << 6) |
| 125 | #define MC13783_CHGOVM (0x1 << 7) |
| 126 | #define MC13783_CHGREVM (0x1 << 8) |
| 127 | #define MC13783_CHGSHORTM (0x1 << 9) |
| 128 | #define MC13783_CCCVM (0x1 << 10) |
| 129 | #define MC13783_CHGCURRM (0x1 << 11) |
| 130 | #define MC13783_BPONIM (0x1 << 12) |
| 131 | #define MC13783_LOBATLM (0x1 << 13) |
| 132 | #define MC13783_LOBATHM (0x1 << 14) |
| 133 | #define MC13783_UDPM (0x1 << 15) |
| 134 | #define MC13783_USB4V4M (0x1 << 16) |
| 135 | #define MC13783_USB2V0M (0x1 << 17) |
| 136 | #define MC13783_USB0V8M (0x1 << 18) |
| 137 | #define MC13783_IDFLOATM (0x1 << 19) |
| 138 | #define MC13783_SE1M (0x1 << 21) |
| 139 | #define MC13783_CKDETM (0x1 << 22) |
| 140 | #define MC13783_UDMM (0x1 << 23) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 141 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 142 | /* INTERRUPT_SENSE0 (2) */ |
| 143 | #define MC13783_CHGDETS (0x1 << 6) |
| 144 | #define MC13783_CHGOVS (0x1 << 7) |
| 145 | #define MC13783_CHGREVS (0x1 << 8) |
| 146 | #define MC13783_CHGSHORTS (0x1 << 9) |
| 147 | #define MC13783_CCCVS (0x1 << 10) |
| 148 | #define MC13783_CHGCURRS (0x1 << 11) |
| 149 | #define MC13783_BPONIS (0x1 << 12) |
| 150 | #define MC13783_LOBATLS (0x1 << 13) |
| 151 | #define MC13783_LOBATHS (0x1 << 14) |
| 152 | #define MC13783_UDPS (0x1 << 15) |
| 153 | #define MC13783_USB4V4S (0x1 << 16) |
| 154 | #define MC13783_USB2V0S (0x1 << 17) |
| 155 | #define MC13783_USB0V8S (0x1 << 18) |
| 156 | #define MC13783_IDFLOATS (0x1 << 19) |
| 157 | #define MC13783_SE1S (0x1 << 21) |
| 158 | #define MC13783_CKDETS (0x1 << 22) |
| 159 | #define MC13783_UDMS (0x1 << 23) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 160 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 161 | /* INTERRUPT_STATUS1 (3) */ |
| 162 | #define MC13783_1HZI (0x1 << 0) |
| 163 | #define MC13783_TODAI (0x1 << 1) |
| 164 | #define MC13783_ONOFD1I (0x1 << 3) /* ON1B */ |
| 165 | #define MC13783_ONOFD2I (0x1 << 4) /* ON2B */ |
| 166 | #define MC13783_ONOFD3I (0x1 << 5) /* ON3B */ |
| 167 | #define MC13783_SYSRSTI (0x1 << 6) |
| 168 | #define MC13783_RTCRSTI (0x1 << 7) |
| 169 | #define MC13783_PCII (0x1 << 8) |
| 170 | #define MC13783_WARMI (0x1 << 9) |
| 171 | #define MC13783_MEMHLDI (0x1 << 10) |
| 172 | #define MC13783_PWRRDYI (0x1 << 11) |
| 173 | #define MC13783_THWARNLI (0x1 << 12) |
| 174 | #define MC13783_THWARNHI (0x1 << 13) |
| 175 | #define MC13783_CLKI (0x1 << 14) |
| 176 | #define MC13783_SEMAFI (0x1 << 15) |
| 177 | #define MC13783_MC2BI (0x1 << 17) |
| 178 | #define MC13783_HSDETI (0x1 << 18) |
| 179 | #define MC13783_HSLI (0x1 << 19) |
| 180 | #define MC13783_ALSPTHI (0x1 << 20) |
| 181 | #define MC13783_AHSSHORTI (0x1 << 21) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 182 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 183 | /* INTERRUPT_MASK1 (4) */ |
| 184 | #define MC13783_1HZM (0x1 << 0) |
| 185 | #define MC13783_TODAM (0x1 << 1) |
| 186 | #define MC13783_ONOFD1M (0x1 << 3) /* ON1B */ |
| 187 | #define MC13783_ONOFD2M (0x1 << 4) /* ON2B */ |
| 188 | #define MC13783_ONOFD3M (0x1 << 5) /* ON3B */ |
| 189 | #define MC13783_SYSRSTM (0x1 << 6) |
| 190 | #define MC13783_RTCRSTM (0x1 << 7) |
| 191 | #define MC13783_PCIM (0x1 << 8) |
| 192 | #define MC13783_WARMM (0x1 << 9) |
| 193 | #define MC13783_MEMHLDM (0x1 << 10) |
| 194 | #define MC13783_PWRRDYM (0x1 << 11) |
| 195 | #define MC13783_THWARNLM (0x1 << 12) |
| 196 | #define MC13783_THWARNHM (0x1 << 13) |
| 197 | #define MC13783_CLKM (0x1 << 14) |
| 198 | #define MC13783_SEMAFM (0x1 << 15) |
| 199 | #define MC13783_MC2BM (0x1 << 17) |
| 200 | #define MC13783_HSDETM (0x1 << 18) |
| 201 | #define MC13783_HSLM (0x1 << 19) |
| 202 | #define MC13783_ALSPTHM (0x1 << 20) |
| 203 | #define MC13783_AHSSHORTM (0x1 << 21) |
| Michael Sevakis | a7af9e4 | 2008-04-12 16:56:45 +0000 | [diff] [blame] | 204 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 205 | /* INTERRUPT_SENSE1 (5) */ |
| 206 | #define MC13783_ONOFD1S (0x1 << 3) /* ON1B */ |
| 207 | #define MC13783_ONOFD2S (0x1 << 4) /* ON2B */ |
| 208 | #define MC13783_ONOFD3S (0x1 << 5) /* ON3B */ |
| 209 | #define MC13783_PWRRDYS (0x1 << 11) |
| 210 | #define MC13783_THWARNLS (0x1 << 12) |
| 211 | #define MC13783_THWARNHS (0x1 << 13) |
| 212 | #define MC13783_CLKS (0x1 << 14) |
| 213 | #define MC13783_MC2BS (0x1 << 17) |
| 214 | #define MC13783_HSDETS (0x1 << 18) |
| 215 | #define MC13783_HSLS (0x1 << 19) |
| 216 | #define MC13783_ALSPTHS (0x1 << 20) |
| 217 | #define MC13783_AHSSHORTS (0x1 << 21) |
| Michael Sevakis | a7af9e4 | 2008-04-12 16:56:45 +0000 | [diff] [blame] | 218 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 219 | /* POWER_UP_MODE_SENSE (6) */ |
| 220 | #define MC13783_ICTESTS (0x1 << 0) |
| 221 | #define MC13783_CLKSELS (0x1 << 1) |
| 222 | #define MC13783_PUMS1S (0x3 << 2) |
| 223 | #define MC13783_PUMS1S_LOW (0x0 << 2) |
| 224 | #define MC13783_PUMS1S_OPEN (0x1 << 2) |
| 225 | #define MC13783_PUMS1S_HIGH (0x2 << 2) |
| 226 | #define MC13783_PUMS2S (0x3 << 4) |
| 227 | #define MC13783_PUMS2S_LOW (0x0 << 4) |
| 228 | #define MC13783_PUMS2S_OPEN (0x1 << 4) |
| 229 | #define MC13783_PUMS2S_HIGH (0x2 << 4) |
| 230 | #define MC13783_PUMS3S (0x3 << 6) |
| 231 | #define MC13783_PUMS3S_LOW (0x0 << 6) |
| 232 | #define MC13783_PUMS3S_OPEN (0x1 << 6) |
| 233 | #define MC13783_PUMS3S_HIGH (0x2 << 6) |
| 234 | #define MC13783_CHRGMOD0S (0x3 << 8) |
| 235 | #define MC13783_CHRGMOD0S_LOW (0x0 << 8) |
| 236 | #define MC13783_CHRGMOD0S_OPEN (0x1 << 8) |
| 237 | #define MC13783_CHRGMOD0S_HIGH (0x3 << 8) |
| 238 | #define MC13783_CHRGMOD1S (0x3 << 10) |
| 239 | #define MC13783_CHRGMOD1S_LOW (0x0 << 10) |
| 240 | #define MC13783_CHRGMOD1S_OPEN (0x1 << 10) |
| 241 | #define MC13783_CHRGMOD1S_HIGH (0x3 << 10) |
| 242 | #define MC13783_UMODS (0x3 << 12) |
| 243 | #define MC13783_UMODS_LOW_UMODS1_LOW (0x0 << 12) |
| 244 | #define MC13783_UMODS_OPEN_UMODS1_LOW (0x1 << 12) |
| 245 | #define MC13783_UMODS_DONTCARE_UMODS1_HIGH (0x2 << 12) |
| 246 | #define MC13783_UMODS_HIGH_UMODS1_LOW (0x3 << 12) |
| 247 | #define MC13783_USBENS (0x1 << 14) |
| 248 | #define MC13783_SW1ABS (0x1 << 15) |
| 249 | #define MC13783_SW2ABS (0x1 << 16) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 250 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 251 | /* IDENTIFICATION (7) */ |
| 252 | #define MC13783_REVISION (0x1f << 0) |
| 253 | #define MC13783_REVISIONr(x) (((x) & MC13783_REVISION) >> 0) |
| 254 | #define MC13783_ICID (0x7 << 6) |
| 255 | #define MC13783_ICIDr(x) (((x) & MC13783_ICID) >> 6) |
| 256 | #define MC13783_FIN (0x3 << 9) |
| 257 | #define MC13783_FINr(x) (((x) & MC13783_FIN) >> 9)) |
| 258 | #define MC13783_FAB (0x3 << 12) |
| 259 | #define MC13783_FABr(x) (((x) & MC13783_FAB) >> 12)) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 260 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 261 | /* SEMAPHORE (8) */ |
| 262 | #define MC13783_SEMCTRLA (0x1 << 0) |
| 263 | #define MC13783_SEMCTRLB (0x1 << 2) |
| 264 | #define MC13783_SEMWRTA (0xf << 4) |
| 265 | #define MC13783_SEMWRTAw(x) (((x) << 4) & MC13783_SEMWRTA) |
| 266 | #define MC13783_SEMWRTAr(x) (((x) & MC13783_SEMWRTA) >> 4) |
| 267 | #define MC13783_SEMWRTB (0x3f << 8) |
| 268 | #define MC13783_SEMWRTBw(x) (((x) << 8) & MC13783_SEMWRTB) |
| 269 | #define MC13783_SEMWRTBr(x) (((x) & MC13783_SEMWRTB) >> 8) |
| 270 | #define MC13783_SEMRDA (0xf << 14) |
| 271 | #define MC13783_SEMRDAw(x) (((x) << 14) & MC13783_SEMRDA) |
| 272 | #define MC13783_SEMRDAr(x) (((x) & MC13783_SEMRDA) >> 14) |
| 273 | #define MC13783_SEMRDB (0x3f << 18) |
| 274 | #define MC13783_SEMRDBw(x) (((x) << 18) & MC13783_SEMRDB) |
| 275 | #define MC13783_SEMRDBr(x) (((x) & MC13783_SEMRDB) >> 18) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 276 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 277 | /* ARBITRATION_PERIPHERAL_AUDIO (9) */ |
| 278 | #define MC13783_AUDIOTXSEL (0x3 << 0) |
| 279 | #define MC13783_AUDIOTXSEL_PRI_SPI (0x0 << 0) |
| 280 | #define MC13783_AUDIOTXSEL_SEC_SPI (0x1 << 0) |
| 281 | #define MC13783_AUDIOTXSEL_OR_SPI (0x2 << 0) |
| 282 | #define MC13783_AUDIOTXSEL_AND_SPI (0x3 << 0) |
| 283 | #define MC13783_TXGAINSEL (0x1 << 2) |
| 284 | #define MC13783_AUDIORXSEL (0x3 << 3) |
| 285 | #define MC13783_AUDIORXSEL_PRI_SPI (0x0 << 3) |
| 286 | #define MC13783_AUDIORXSEL_SEC_SPI (0x1 << 3) |
| 287 | #define MC13783_AUDIORXSEL_OR_SPI (0x2 << 3) |
| 288 | #define MC13783_AUDIORXSEL_AND_SPI (0x3 << 3) |
| 289 | #define MC13783_RXGAINSEL (0x1 << 5) |
| 290 | #define MC13783_AUDIOCDCSEL (0x1 << 6) |
| 291 | #define MC13783_AUDIOSTDCSEL (0x1 << 7) |
| 292 | #define MC13783_BIASSEL (0x3 << 8) |
| 293 | #define MC13783_BIASSEL_PRI_SPI (0x0 << 8) |
| 294 | #define MC13783_BIASSEL_SEC_SPI (0x1 << 8) |
| 295 | #define MC13783_BIASSEL_OR_SPI (0x2 << 8) |
| 296 | #define MC13783_BIASSEL_AND_SPI (0x3 << 8) |
| 297 | #define MC13783_RTCSEL (0x1 << 11) |
| 298 | #define MC13783_ADCSEL (0x3 << 12) |
| 299 | #define MC13783_ADCSEL_PRI1_SEC1 (0x0 << 12) |
| 300 | #define MC13783_ADCSEL_PRI2_SEC0 (0x1 << 12) |
| 301 | #define MC13783_ADCSEL_PRI0_SEC2 (0x2 << 12) |
| 302 | /* 0x3 = same as 0x0 */ |
| 303 | #define MC13783_USBSEL (0x1 << 14) |
| 304 | #define MC13783_CHRGSEL (0x1 << 15) |
| 305 | #define MC13783_BLLEDSEL (0x1 << 16) |
| 306 | #define MC13783_TCLEDSEL (0x1 << 17) |
| 307 | #define MC13783_ADAPTSEL (0x1 << 18) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 308 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 309 | /* ARBITRATION_SWITCHERS (10) */ |
| 310 | #define MC13783_SW1ASTBYAND (0x1 << 0) |
| 311 | #define MC13783_SW1BSTBYAND (0x1 << 1) |
| 312 | #define MC13783_SW2ASTBYAND (0x1 << 2) |
| 313 | #define MC13783_SW2BSTBYAND (0x1 << 3) |
| 314 | #define MC13783_SW3SEL0 (0x1 << 4) |
| 315 | #define MC13783_SW1ABDVS (0x1 << 5) |
| 316 | #define MC13783_SW2ABDVS (0x1 << 6) |
| 317 | #define MC13783_SW1ASEL (0x1 << 7) |
| 318 | #define MC13783_SW1BSEL (0x1 << 8) |
| 319 | #define MC13783_SW2ASEL (0x1 << 9) |
| 320 | #define MC13783_SW2BSEL (0x1 << 10) |
| 321 | #define MC13783_PLLSEL (0x1 << 12) |
| 322 | #define MC13783_PWGT1SEL (0x1 << 14) |
| 323 | #define MC13783_PWGT2SEL (0x1 << 15) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 324 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 325 | /* ARBITRATION_REGULATORS0 (11) */ |
| 326 | #define MC13783_VAUDIOSEL (0x3 << 0) |
| 327 | #define MC13783_VAUDIOSEL_PRI (0x0 << 0) |
| 328 | #define MC13783_VIOHISEL (0x3 << 2) |
| 329 | #define MC13783_VIOHISEL_PRI (0x0 << 2) |
| 330 | #define MC13783_VIOLOSEL (0x3 << 4) |
| 331 | #define MC13783_VIOLOSEL_PRI (0x0 << 4) |
| 332 | #define MC13783_VDIGSEL (0x3 << 6) |
| 333 | #define MC13783_VDIGSEL_PRI (0x0 << 6) |
| 334 | #define MC13783_VGENSEL (0x3 << 8) |
| 335 | #define MC13783_VGENSEL_PRI (0x0 << 8) |
| 336 | #define MC13783_VRFDIGSEL (0x3 << 10) |
| 337 | #define MC13783_VRFDIGSEL_PRI (0x0 << 10) |
| 338 | #define MC13783_VRFREFSEL (0x3 << 12) |
| 339 | #define MC13783_VRFREFSEL_PRI (0x0 << 12) |
| 340 | #define MC13783_VRFCPSEL (0x3 << 14) |
| 341 | #define MC13783_VRFCPSEL_PRI (0x0 << 14) |
| 342 | #define MC13783_VSIMSEL (0x3 << 16) |
| 343 | #define MC13783_VSIMSEL_PRI (0x0 << 16) |
| 344 | #define MC13783_VESIMSEL (0x3 << 18) |
| 345 | #define MC13783_VESIMSEL_PRI (0x0 << 18) |
| 346 | #define MC13783_VCAMSEL (0x3 << 20) |
| 347 | #define MC13783_VCAMSEL_PRI (0x0 << 20) |
| 348 | #define MC13783_VRFBGSEL (0x3 << 22) |
| 349 | #define MC13783_VRFBGSEL_PRI (0x0 << 22) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 350 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 351 | /* ARBITRATION_REGULATORS1 (12) */ |
| 352 | #define MC13783_VVIBSEL (0x3 << 0) |
| 353 | #define MC13783_VVIBSEL_PRI (0x0 << 0) |
| 354 | #define MC13783_VRF1SEL (0x3 << 2) |
| 355 | #define MC13783_VRF1SEL_PRI (0x0 << 2) |
| 356 | #define MC13783_VRF2SEL (0x3 << 4) |
| 357 | #define MC13783_VRF2SEL_PRI (0x0 << 4) |
| 358 | #define MC13783_VMMC1SEL (0x3 << 6) |
| 359 | #define MC13783_VMMC1SEL_PRI (0x0 << 6) |
| 360 | #define MC13783_VMMC2SEL (0x3 << 8) |
| 361 | #define MC13783_VMMC2SEL_PRI (0x0 << 8) |
| 362 | #define MC13783_GPO1SEL (0x3 << 14) |
| 363 | #define MC13783_GPO1SEL_PRI (0x0 << 14) |
| 364 | #define MC13783_GPO1SEL_BOTH (0x1 << 14) |
| 365 | #define MC13783_GPO1SEL_AND (0x3 << 14) |
| 366 | #define MC13783_GPO2SEL (0x3 << 16) |
| 367 | #define MC13783_GPO2SEL_PRI (0x0 << 16) |
| 368 | #define MC13783_GPO2SEL_BOTH (0x1 << 16) |
| 369 | #define MC13783_GPO2SEL_AND (0x3 << 16) |
| 370 | #define MC13783_GPO3SEL (0x3 << 18) |
| 371 | #define MC13783_GPO3SEL_PRI (0x0 << 18) |
| 372 | #define MC13783_GPO3SEL_BOTH (0x1 << 18) |
| 373 | #define MC13783_GPO3SEL_AND (0x3 << 18) |
| 374 | #define MC13783_GPO4SEL (0x3 << 20) |
| 375 | #define MC13783_GPO4SEL_PRI (0x0 << 20) |
| 376 | #define MC13783_GPO4SEL_BOTH (0x1 << 20) |
| 377 | #define MC13783_GPO4SEL_AND (0x3 << 20) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 378 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 379 | /* POWER_CONTROL0 (13) */ |
| 380 | #define MC13783_PCEN (0x1 << 0) |
| 381 | #define MC13783_PCCOUNTEN (0x1 << 1) |
| 382 | #define MC13783_WARMEN (0x1 << 2) |
| 383 | #define MC13783_USEROFFSPI (0x1 << 3) |
| 384 | #define MC13783_USEROFFPC (0x1 << 4) |
| 385 | #define MC13783_USEROFFCLK (0x1 << 5) |
| 386 | #define MC13783_CLK32KMCUEN (0x1 << 6) |
| 387 | #define MC13783_VBKUP2AUTOMH (0x1 << 7) |
| 388 | #define MC13783_VBKUP1EN (0x1 << 8) |
| 389 | #define MC13783_VBKUPAUTO (0x1 << 9) |
| 390 | #define MC13783_VBKUP1 (0x3 << 10) |
| 391 | #define MC13783_VBKUP1_1_0V (0x0 << 10) |
| 392 | #define MC13783_VBKUP1_1_2V (0x1 << 10) |
| 393 | #define MC13783_VBKUP1_1_575V (0x2 << 10) |
| 394 | #define MC13783_VBKUP1_1_8V (0x3 << 10) |
| 395 | #define MC13783_VBKUP2EN (0x1 << 12) |
| 396 | #define MC13783_VBKUP2AUTO (0x1 << 13) |
| 397 | #define MC13783_VBKUP2 (0x3 << 14) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 398 | #define MC13783_VBKUP2_1_0V (0x0 << 14) |
| 399 | #define MC13783_VBKUP2_1_2V (0x1 << 14) |
| 400 | #define MC13783_VBKUP2_1_5V (0x2 << 14) |
| 401 | #define MC13783_VBKUP2_1_8V (0x3 << 14) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 402 | #define MC13783_BPDET (0x3 << 16) |
| 403 | /* 00: UVDET 2.6, LOBATL UVDET+0.2, LOBATH UVDET+0.4 BPON 3.2 */ |
| 404 | #define MC13783_BPDET_2_4 (0x0 << 16) |
| 405 | /* 01: UVDET 2.6, LOBATL UVDET+0.3, LOBATH UVDET+0.5 BPON 3.2 */ |
| 406 | #define MC13783_BPDET_3_5 (0x1 << 16) |
| 407 | /* 10: UVDET 2.6, LOBATL UVDET+0.4, LOBATH UVDET+0.7 BPON 3.2 */ |
| 408 | #define MC13783_BPDET_4_7 (0x2 << 16) |
| 409 | /* 11: UVDET 2.6, LOBATL UVDET+0.5, LOBATH UVDET+0.8 BPON 3.2 */ |
| 410 | #define MC13783_BPDET_5_8 (0x3 << 16) |
| 411 | #define MC13783_EOLSEL (0x1 << 18) |
| 412 | #define MC13783_BATTDETEN (0x1 << 19) |
| 413 | #define MC13783_VCOIN (0x7 << 20) |
| 414 | #define MC13783_VCOIN_2_50V (0x0 << 20) |
| 415 | #define MC13783_VCOIN_2_70V (0x1 << 20) |
| 416 | #define MC13783_VCOIN_2_80V (0x2 << 20) |
| 417 | #define MC13783_VCOIN_2_90V (0x3 << 20) |
| 418 | #define MC13783_VCOIN_3_00V (0x4 << 20) |
| 419 | #define MC13783_VCOIN_3_10V (0x5 << 20) |
| 420 | #define MC13783_VCOIN_3_20V (0x6 << 20) |
| 421 | #define MC13783_VCOIN_3_30V (0x7 << 20) |
| 422 | #define MC13783_COINCHEN (0x1 << 23) |
| 423 | |
| 424 | /* POWER_CONTROL1 (14) */ |
| 425 | #define MC13783_PCT (0xff << 0) |
| 426 | /* Up to 8 seconds */ |
| 427 | #define MC13783_PCTw(x) (((x) << 0) & MC13783_PCT) |
| 428 | #define MC13783_PCTr(x) (((x) & MC13783_PCT) >> 0) |
| 429 | #define MC13783_PCCOUNT (0xf << 8) |
| 430 | #define MC13783_PCCOUNTw(x) (((x) << 8) & MC13783_PCCOUNT) |
| 431 | #define MC13783_PCCOUNTr(x) (((x) & MC13783_PCCOUNT) >> 8) |
| 432 | #define MC13783_PCMAXCNT (0xf << 12) |
| 433 | #define MC13783_PCMAXCNTw(x) (((x) << 12) & MC13783_PCMAXCNT) |
| 434 | #define MC13783_PCMAXCNTr(x) (((x) & MC13783_PCMAXCNT) >> 12) |
| 435 | #define MC13783_MEMTMR (0xf << 16) |
| 436 | /* Up to 8 minutes with MEMALLON=0, <> 0 + MEMALLON=1: infinite */ |
| 437 | #define MC13783_MEMTMRw(x) (((x) << 16) & MC13783_MEMTMR) |
| 438 | #define MC13783_MEMTMRr(x) (((x) & MC13783_MEMTMR) >> 16) |
| 439 | #define MC13783_MEMALLON (0x1 << 20) |
| 440 | |
| 441 | /* POWER_CONTROL2 (15) */ |
| 442 | #define MC13783_RESTARTEN (0x1 << 0) |
| 443 | #define MC13783_ON1BRSTEN (0x1 << 1) |
| 444 | #define MC13783_ON2BRSTEN (0x1 << 2) |
| 445 | #define MC13783_ON3BTSTEN (0x1 << 3) |
| 446 | #define MC13783_ON1BDBNC (0x3 << 4) |
| 447 | #define MC13783_ON1BDBNC_0MS (0x0 << 4) |
| 448 | #define MC13783_ON1BDBNC_30MS (0x1 << 4) |
| 449 | #define MC13783_ON1BDBNC_150MS (0x2 << 4) |
| 450 | #define MC13783_ON1BDBNC_750MS (0x3 << 4) |
| 451 | #define MC13783_ON2BDBNC (0x3 << 6) |
| 452 | #define MC13783_ON2BDBNC_0MS (0x0 << 6) |
| 453 | #define MC13783_ON2BDBNC_30MS (0x1 << 6) |
| 454 | #define MC13783_ON2BDBNC_150MS (0x2 << 6) |
| 455 | #define MC13783_ON2BDBNC_750MS (0x3 << 6) |
| 456 | #define MC13783_ON3BDBNC (0x3 << 8) |
| 457 | #define MC13783_ON3BDBNC_0MS (0x0 << 8) |
| 458 | #define MC13783_ON3BDBNC_30MS (0x1 << 8) |
| 459 | #define MC13783_ON3BDBNC_150MS (0x2 << 8) |
| 460 | #define MC13783_ON3BDBNC_750MS (0x3 << 8) |
| 461 | #define MC13783_STANDBYPRIINV (0x1 << 10) |
| 462 | #define MC13783_STANDBYSECINV (0x1 << 11) |
| 463 | |
| 464 | /* REGEN_ASSIGNMENT (16) */ |
| 465 | #define MC13783_VAUDIOREGEN (0x1 << 0) |
| 466 | #define MC13783_VIOHIREGEN (0x1 << 1) |
| 467 | #define MC13783_VIOLOREGEN (0x1 << 2) |
| 468 | #define MC13783_VDIGREGEN (0x1 << 3) |
| 469 | #define MC13783_VGENREGEN (0x1 << 4) |
| 470 | #define MC13783_VRFDIGREGEN (0x1 << 5) |
| 471 | #define MC13783_VRFREFREGEN (0x1 << 6) |
| 472 | #define MC13783_VRFCPREGEN (0x1 << 7) |
| 473 | #define MC13783_VCAMREGEN (0x1 << 8) |
| 474 | #define MC13783_VRFBGREGEN (0x1 << 9) |
| 475 | #define MC13783_VRF1REGEN (0x1 << 10) |
| 476 | #define MC13783_VRF2REGEN (0x1 << 11) |
| 477 | #define MC13783_VMMC1REGEN (0x1 << 12) |
| 478 | #define MC13783_VMMC2REGEN (0x1 << 13) |
| 479 | #define MC13783_GPO1REGEN (0x1 << 16) |
| 480 | #define MC13783_GPO2REGEN (0x1 << 17) |
| 481 | #define MC13783_GPO3REGEN (0x1 << 18) |
| 482 | #define MC13783_GPO4REGEN (0x1 << 19) |
| 483 | #define MC13783_REGENINV (0x1 << 20) |
| 484 | #define MC13783_VESIMESIMEN (0x1 << 21) |
| 485 | #define MC13783_VMMC1ESIMEN (0x1 << 22) |
| 486 | #define MC13783_VMMC2ESIMEN (0x1 << 23) |
| 487 | |
| 488 | /* MEMORYA (18) */ |
| 489 | #define MC13783_MEMORYA_MASK (0xffffff) |
| 490 | |
| 491 | /* MEMORYB (19) */ |
| 492 | #define MC13783_MEMORYB_MASK (0xffffff) |
| 493 | |
| 494 | /* RTC_TIME (20) */ |
| 495 | #define MC13783_RTC_TIME_MASK (0x1ffff) |
| 496 | |
| 497 | /* RTC_ALARM (21) */ |
| 498 | #define MC13783_RTC_ALARM_MASK (0x1ffff) |
| 499 | |
| 500 | /* RTC_DAY (22) */ |
| 501 | #define MC13783_RTC_DAY_MASK (0x7fff) |
| 502 | |
| 503 | /* RTC_DAY_ALARM (23) */ |
| 504 | #define MC13783_RTC_DAY_ALARM_MASK (0x7fff) |
| 505 | |
| 506 | /* SWITCHERS0 (24) */ |
| 507 | #define MC13783_SW1A (0x3f << 0) |
| 508 | #define MC13783_SW1Aw(x) (((x) << 0) & MC13783_SW1A) |
| 509 | #define MC13783_SW1Ar(x) (((x) & MC13783_SW1A) >> 0) |
| 510 | #define MC13783_SW1ADVS (0x3f << 6) |
| 511 | #define MC13783_SW1ADVSw(x) (((x) << 6) & MC13783_SW1ADVS) |
| 512 | #define MC13783_SW1ADVSr(x) (((x) & MC13783_SW1ADVS) >> 6) |
| 513 | #define MC13783_SW1ASTBY (0x3f << 12) |
| 514 | #define MC13783_SW1ASTBYw(x) (((x) << 12) & MC13783_SW1ASTBY) |
| 515 | #define MC13783_SW1ASTBYr(x) (((x) & MC13783_SW1ASTBY) >> 12) |
| 516 | |
| 517 | /* SWITCHERS1 (25) */ |
| 518 | #define MC13783_SW1B (0x3f << 0) |
| 519 | #define MC13783_SW1Bw(x) (((x) << 0) & MC13783_SW1B) |
| 520 | #define MC13783_SW1Br(x) (((x) & MC13783_SW1B) >> 0) |
| 521 | #define MC13783_SW1BDVS (0x3f << 6) |
| 522 | #define MC13783_SW1BDVSw(x) (((x) << 6) & MC13783_SW1BDVS) |
| 523 | #define MC13783_SW1BDVSr(x) (((x) & MC13783_SW1BDVS) >> 6) |
| 524 | #define MC13783_SW1BSTBY (0x3f << 12) |
| 525 | #define MC13783_SW1BSTBYw(x) (((x) << 12) & MC13783_SW1BSTBY) |
| 526 | #define MC13783_SW1BSTBYr(x) (((x) & MC13783_SW1BSTBY) >> 12) |
| 527 | |
| 528 | /* SWITCHERS2 (26) */ |
| 529 | #define MC13783_SW2A (0x3f << 0) |
| 530 | #define MC13783_SW2Aw(x) (((x) << 0) & MC13783_SW1A) |
| 531 | #define MC13783_SW2Ar(x) (((x) & MC13783_SW1A) >> 0) |
| 532 | #define MC13783_SW2ADVS (0x3f << 6) |
| 533 | #define MC13783_SW2ADVSw(x) (((x) << 6) & MC13783_SW2ADVS) |
| 534 | #define MC13783_SW2ADVSr(x) (((x) & MC13783_SW2ADVS) >> 6) |
| 535 | #define MC13783_SW2ASTBY (0x3f << 12) |
| 536 | #define MC13783_SW2ASTBYw(x) (((x) << 12) & MC13783_SW2ASTBY) |
| 537 | #define MC13783_SW2ASTBYr(x) (((x) & MC13783_SW2ASTBY) >> 12) |
| 538 | |
| 539 | /* SWITCHERS3 (27) */ |
| 540 | #define MC13783_SW2B (0x3f << 0) |
| 541 | #define MC13783_SW2Bw(x) (((x) << 0) & MC13783_SW2B) |
| 542 | #define MC13783_SW2Br(x) (((x) & MC13783_SW2B) >> 0) |
| 543 | #define MC13783_SW2BDVS (0x3f << 6) |
| 544 | #define MC13783_SW2BDVSw(x) (((x) << 6) & MC13783_SW2BDVS) |
| 545 | #define MC13783_SW2BDVSr(x) (((x) & MC13783_SW2BDVS) >> 6) |
| 546 | #define MC13783_SW2BSTBY (0x3f << 12) |
| 547 | #define MC13783_SW2BSTBYw(x) (((x) << 12) & MC13783_SW2BSTBY) |
| 548 | #define MC13783_SW2BSTBYr(x) (((x) & MC13783_SW2BSTBY) >> 12) |
| 549 | |
| 550 | /* SWITCHERS4 (28) */ |
| 551 | #define MC13783_SW1AMODE (0x3 << 0) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 552 | #define MC13783_SW1AMODE_OFF (0x0 << 0) |
| 553 | #define MC13783_SW1AMODE_PWM (0x1 << 0) |
| 554 | #define MC13783_SW1AMODE_PWM_SKIP (0x2 << 0) |
| 555 | #define MC13783_SW1AMODE_PFM (0x3 << 0) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 556 | #define MC13783_SW1ASTBYMODE (0x3 << 2) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 557 | #define MC13783_SW1ASTBYMODE_OFF (0x0 << 2) |
| 558 | #define MC13783_SW1ASTBYMODE_PWM (0x1 << 2) |
| 559 | #define MC13783_SW1ASTBYMODE_PWM_SKIP (0x2 << 2) |
| 560 | #define MC13783_SW1ASTBYMODE_PFM (0x3 << 2) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 561 | #define MC13783_SW1ADVSSPEED (0x3 << 6) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 562 | /* 25mV every ... */ |
| 563 | #define MC13783_SW1ADVSSPEED_4US_NO_PWR_RDY (0x0 << 6) |
| 564 | #define MC13783_SW1ADVSSPEED_4US (0x1 << 6) |
| 565 | #define MC13783_SW1ADVSSPEED_8US (0x2 << 6) |
| 566 | #define MC13783_SW1ADVSSPEED_16US (0x3 << 6) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 567 | #define MC13783_SW1APANIC (0x1 << 8) |
| 568 | #define MC13783_SW1ASFST (0x1 << 9) |
| 569 | #define MC13783_SW1BMODE (0x3 << 10) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 570 | #define MC13783_SW1BMODE_OFF (0x0 << 10) |
| 571 | #define MC13783_SW1BMODE_PWM (0x1 << 10) |
| 572 | #define MC13783_SW1BMODE_PWM_SKIP (0x2 << 10) |
| 573 | #define MC13783_SW1BMODE_PFM (0x3 << 10) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 574 | #define MC13783_SW1BSTBYMODE (0x3 << 12) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 575 | #define MC13783_SW1BSTBYMODE_OFF (0x0 << 12) |
| 576 | #define MC13783_SW1BSTBYMODE_PWM (0x1 << 12) |
| 577 | #define MC13783_SW1BSTBYMODE_PWM_SKIP (0x2 << 12) |
| 578 | #define MC13783_SW1BSTBYMODE_PFM (0x3 << 12) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 579 | #define MC13783_SW1BDVSSPEED (0x3 << 14) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 580 | /* 25mV every ... */ |
| 581 | #define MC13783_SW1BDVSSPEED_4US_NO_PWR_RDY (0x0 << 14) |
| 582 | #define MC13783_SW1BDVSSPEED_4US (0x1 << 14) |
| 583 | #define MC13783_SW1BDVSSPEED_8US (0x2 << 14) |
| 584 | #define MC13783_SW1BDVSSPEED_16US (0x3 << 14) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 585 | #define MC13783_SW1BPANIC (0x1 << 16) |
| 586 | #define MC13783_SW1BSFST (0x1 << 17) |
| 587 | #define MC13783_PLLEN (0x1 << 18) |
| 588 | #define MC13783_PLLX (0x7 << 19) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 589 | #define MC13783_PLLX_28 (0x0 << 19) |
| 590 | #define MC13783_PLLX_29 (0x1 << 19) |
| 591 | #define MC13783_PLLX_30 (0x2 << 19) |
| 592 | #define MC13783_PLLX_31 (0x3 << 19) |
| 593 | #define MC13783_PLLX_32 (0x4 << 19) |
| 594 | #define MC13783_PLLX_33 (0x5 << 19) |
| 595 | #define MC13783_PLLX_34 (0x6 << 19) |
| 596 | #define MC13783_PLLX_35 (0x7 << 19) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 597 | |
| 598 | /* SWITCHERS5 (29) */ |
| 599 | #define MC13783_SW2AMODE (0x3 << 0) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 600 | #define MC13783_SW2AMODE_OFF (0x0 << 0) |
| 601 | #define MC13783_SW2AMODE_PWM (0x1 << 0) |
| 602 | #define MC13783_SW2AMODE_PWM_SKIP (0x2 << 0) |
| 603 | #define MC13783_SW2AMODE_PFM (0x3 << 0) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 604 | #define MC13783_SW2ASTBYMODE (0x3 << 2) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 605 | #define MC13783_SW2ASTBYMODE_OFF (0x0 << 2) |
| 606 | #define MC13783_SW2ASTBYMODE_PWM (0x1 << 2) |
| 607 | #define MC13783_SW2ASTBYMODE_PWM_SKIP (0x2 << 2) |
| 608 | #define MC13783_SW2ASTBYMODE_PFM (0x3 << 2) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 609 | #define MC13783_SW2ADVSSPEED (0x3 << 6) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 610 | #define MC13783_SW2ADVSSPEED_4US_NO_PWR_RDY (0x0 << 6) |
| 611 | #define MC13783_SW2ADVSSPEED_4US (0x1 << 6) |
| 612 | #define MC13783_SW2ADVSSPEED_8US (0x2 << 6) |
| 613 | #define MC13783_SW2ADVSSPEED_16US (0x3 << 6) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 614 | #define MC13783_SW2APANIC (0x1 << 8) |
| 615 | #define MC13783_SW2ASFST (0x1 << 9) |
| 616 | #define MC13783_SW2BMODE (0x3 << 10) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 617 | #define MC13783_SW2BMODE_OFF (0x0 << 10) |
| 618 | #define MC13783_SW2BMODE_PWM (0x1 << 10) |
| 619 | #define MC13783_SW2BMODE_PWM_SKIP (0x2 << 10) |
| 620 | #define MC13783_SW2BMODE_PFM (0x3 << 10) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 621 | #define MC13783_SW2BSTBYMODE (0x3 << 12) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 622 | #define MC13783_SW2BSTBYMODE_OFF (0x0 << 12) |
| 623 | #define MC13783_SW2BSTBYMODE_PWM (0x1 << 12) |
| 624 | #define MC13783_SW2BSTBYMODE_PWM_SKIP (0x2 << 12) |
| 625 | #define MC13783_SW2BSTBYMODE_PFM (0x3 << 12) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 626 | #define MC13783_SW2BDVSSPEED (0x3 << 14) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 627 | #define MC13783_SW2BDVSSPEED_4US_NO_PWR_RDY (0x0 << 14) |
| 628 | #define MC13783_SW2BDVSSPEED_4US (0x1 << 14) |
| 629 | #define MC13783_SW2BDVSSPEED_8US (0x2 << 14) |
| 630 | #define MC13783_SW2BDVSSPEED_16US (0x3 << 14) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 631 | #define MC13783_SW2BPANIC (0x1 << 16) |
| 632 | #define MC13783_SW2BSFST (0x1 << 17) |
| 633 | #define MC13783_SW3 (0x3 << 18) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 634 | #define MC13783_SW3_5_0V (0x0 << 18) |
| 635 | /* 0x1...0x2 same as 0x0 */ |
| 636 | #define MC13783_SW3_5_5V (0x3 << 18) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 637 | #define MC13783_SW3EN (0x1 << 20) |
| 638 | #define MC13783_SW3STBY (0x1 << 21) |
| 639 | #define MC13783_SW3MODE (0x1 << 22) |
| 640 | |
| 641 | /* REGULATOR_SETTING0 (30) */ |
| 642 | #define MC13783_VIOLO (0x3 << 2) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 643 | #define MC13783_VIOLO_1_20V (0x0 << 2) |
| 644 | #define MC13783_VIOLO_1_30V (0x1 << 2) |
| 645 | #define MC13783_VIOLO_1_50V (0x2 << 2) |
| 646 | #define MC13783_VIOLO_1_80V (0x3 << 2) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 647 | #define MC13783_VDIG (0x3 << 4) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 648 | #define MC13783_VDIG_1_20V (0x0 << 4) |
| 649 | #define MC13783_VDIG_1_30V (0x1 << 4) |
| 650 | #define MC13783_VDIG_1_50V (0x2 << 4) |
| 651 | #define MC13783_VDIG_1_80V (0x3 << 4) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 652 | #define MC13783_VGEN (0x7 << 6) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 653 | #define MC13783_VGEN_1_20V (0x0 << 6) |
| 654 | #define MC13783_VGEN_1_30V (0x1 << 6) |
| 655 | #define MC13783_VGEN_1_50V (0x2 << 6) |
| 656 | #define MC13783_VGEN_1_80V (0x3 << 6) |
| 657 | #define MC13783_VGEN_1_10V (0x4 << 6) |
| 658 | #define MC13783_VGEN_2_00V (0x5 << 6) |
| 659 | #define MC13783_VGEN_2_775V (0x6 << 6) |
| 660 | #define MC13783_VGEN_2_40V (0x7 << 6) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 661 | #define MC13783_VRFDIG (0x3 << 9) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 662 | #define MC13783_VREFDIG_1_20V (0x0 << 9) |
| 663 | #define MC13783_VREFDIG_1_30V (0x1 << 9) |
| 664 | #define MC13783_VREFDIG_1_80V (0x2 << 9) |
| 665 | #define MC13783_VREFDIG_1_875V (0x3 << 9) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 666 | #define MC13783_VRFREF (0x3 << 11) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 667 | #define MC13783_VRFREF_2_475V (0x0 << 11) |
| 668 | #define MC13783_VRFREF_2_600V (0x1 << 11) |
| 669 | #define MC13783_VRFREF_2_700V (0x2 << 11) |
| 670 | #define MC13783_VRFREF_2_775V (0x3 << 11) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 671 | #define MC13783_VRFCP (0x1 << 13) |
| 672 | #define MC13783_VSIM (0x1 << 14) |
| 673 | #define MC13783_VESIM (0x1 << 15) |
| 674 | #define MC13783_VCAM (0x7 << 16) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 675 | #define MC13783_VCAM_1_50V (0x0 << 16) |
| 676 | #define MC13783_VCAM_1_80V (0x1 << 16) |
| 677 | #define MC13783_VCAM_2_50V (0x2 << 16) |
| 678 | #define MC13783_VCAM_2_55V (0x3 << 16) |
| 679 | #define MC13783_VCAM_2_60V (0x4 << 16) |
| 680 | #define MC13783_VCAM_2_75V (0x5 << 16) |
| 681 | #define MC13783_VCAM_2_80V (0x6 << 16) |
| 682 | #define MC13783_VCAM_3_00V (0x7 << 16) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 683 | |
| 684 | /* REGULATOR_SETTING1 (31) */ |
| 685 | #define MC13783_VVIB (0x3 << 0) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 686 | #define MC13783_VVIB_1_30V (0x0 << 0) |
| 687 | #define MC13783_VVIB_1_80V (0x1 << 0) |
| 688 | #define MC13783_VVIB_2_00V (0x2 << 0) |
| 689 | #define MC13783_VVIB_3_00V (0x3 << 0) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 690 | #define MC13783_VRF1 (0x3 << 2) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 691 | #define MC13783_VRF1_1_500V (0x0 << 2) |
| 692 | #define MC13783_VRF1_1_875V (0x1 << 2) |
| 693 | #define MC13783_VRF1_2_700V (0x2 << 2) |
| 694 | #define MC13783_VRF1_2_775V (0x3 << 2) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 695 | #define MC13783_VRF2 (0x3 << 4) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 696 | #define MC13783_VRF2_1_500V (0x0 << 4) |
| 697 | #define MC13783_VRF2_1_875V (0x1 << 4) |
| 698 | #define MC13783_VRF2_2_700V (0x2 << 4) |
| 699 | #define MC13783_VRF2_2_775V (0x3 << 4) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 700 | #define MC13783_VMMC1 (0x7 << 6) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 701 | #define MC13783_VMMC1_1_60V (0x0 << 6) |
| 702 | #define MC13783_VMMC1_1_80V (0x1 << 6) |
| 703 | #define MC13783_VMMC1_2_00V (0x2 << 6) |
| 704 | #define MC13783_VMMC1_2_60V (0x3 << 6) |
| 705 | #define MC13783_VMMC1_2_70V (0x4 << 6) |
| 706 | #define MC13783_VMMC1_2_80V (0x5 << 6) |
| 707 | #define MC13783_VMMC1_2_90V (0x6 << 6) |
| 708 | #define MC13783_VMMC1_3_00V (0x7 << 6) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 709 | #define MC13783_VMMC2 (0x7 << 9) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 710 | #define MC13783_VMMC2_1_60V (0x0 << 9) |
| 711 | #define MC13783_VMMC2_1_80V (0x1 << 9) |
| 712 | #define MC13783_VMMC2_2_00V (0x2 << 9) |
| 713 | #define MC13783_VMMC2_2_60V (0x3 << 9) |
| 714 | #define MC13783_VMMC2_2_70V (0x4 << 9) |
| 715 | #define MC13783_VMMC2_2_80V (0x5 << 9) |
| 716 | #define MC13783_VMMC2_2_90V (0x6 << 9) |
| 717 | #define MC13783_VMMC2_3_00V (0x7 << 9) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 718 | |
| 719 | /* REGULATOR_MODE0 (32) */ |
| 720 | #define MC13783_VAUDIOEN (0x1 << 0) |
| 721 | #define MC13783_VAUDIOSTBY (0x1 << 1) |
| 722 | #define MC13783_VAUDIOMODE (0x1 << 2) |
| 723 | #define MC13783_VIOHIEN (0x1 << 3) |
| 724 | #define MC13783_VIOHISTBY (0x1 << 4) |
| 725 | #define MC13783_VIOHIMODE (0x1 << 5) |
| 726 | #define MC13783_VIOLOEN (0x1 << 6) |
| 727 | #define MC13783_VIOLOSTBY (0x1 << 7) |
| 728 | #define MC13783_VIOLOMODE (0x1 << 8) |
| 729 | #define MC13783_VDIGEN (0x1 << 9) |
| 730 | #define MC13783_VDIGSTBY (0x1 << 10) |
| 731 | #define MC13783_VDIGMODE (0x1 << 11) |
| 732 | #define MC13783_VGENEN (0x1 << 12) |
| 733 | #define MC13783_VGENSTBY (0x1 << 13) |
| 734 | #define MC13783_VGENMODE (0x1 << 14) |
| 735 | #define MC13783_VRFDIGEN (0x1 << 15) |
| 736 | #define MC13783_VRFDIGSTBY (0x1 << 16) |
| 737 | #define MC13783_VRFDIGMODE (0x1 << 17) |
| 738 | #define MC13783_VRFREFEN (0x1 << 18) |
| 739 | #define MC13783_VRFREFSTBY (0x1 << 19) |
| 740 | #define MC13783_VRFREFMODE (0x1 << 20) |
| 741 | #define MC13783_VRFCPEN (0x1 << 21) |
| 742 | #define MC13783_VRFCPSTBY (0x1 << 22) |
| 743 | #define MC13783_VRFCPMODE (0x1 << 23) |
| 744 | |
| 745 | /* REGULATOR_MODE1 (33) */ |
| 746 | #define MC13783_VSIMEN (0x1 << 0) |
| 747 | #define MC13783_VSIMSTBY (0x1 << 1) |
| 748 | #define MC13783_VSIMMODE (0x1 << 2) |
| 749 | #define MC13783_VESIMEN (0x1 << 3) |
| 750 | #define MC13783_VESIMSTBY (0x1 << 4) |
| 751 | #define MC13783_VESIMMODE (0x1 << 5) |
| 752 | #define MC13783_VCAMEN (0x1 << 6) |
| 753 | #define MC13783_VCAMSTBY (0x1 << 7) |
| 754 | #define MC13783_VCAMMODE (0x1 << 8) |
| 755 | #define MC13783_VRFBGEN (0x1 << 9) |
| 756 | #define MC13783_VRFBGSTBY (0x1 << 10) |
| 757 | #define MC13783_VVIBEN (0x1 << 11) |
| 758 | #define MC13783_VRF1EN (0x1 << 12) |
| 759 | #define MC13783_VRF1STBY (0x1 << 13) |
| 760 | #define MC13783_VRF1MODE (0x1 << 14) |
| 761 | #define MC13783_VRF2EN (0x1 << 15) |
| 762 | #define MC13783_VRF2STBY (0x1 << 16) |
| 763 | #define MC13783_VRF2MODE (0x1 << 17) |
| 764 | #define MC13783_VMMC1EN (0x1 << 18) |
| 765 | #define MC13783_VMMC1STBY (0x1 << 19) |
| 766 | #define MC13783_VMMC1MODE (0x1 << 20) |
| 767 | #define MC13783_VMMC2EN (0x1 << 21) |
| 768 | #define MC13783_VMMC2STBY (0x1 << 22) |
| 769 | #define MC13783_VMMC2MODE (0x1 << 23) |
| 770 | |
| 771 | /* POWER_MISCELLANEOUS (34) */ |
| 772 | #define MC13783_GPO1EN (0x1 << 6) |
| 773 | #define MC13783_GPO1STBY (0x1 << 7) |
| 774 | #define MC13783_GPO2EN (0x1 << 8) |
| 775 | #define MC13783_GPO2STBY (0x1 << 9) |
| 776 | #define MC13783_GPO3EN (0x1 << 10) |
| 777 | #define MC13783_GPO3STBY (0x1 << 11) |
| 778 | #define MC13783_GPO4EN (0x1 << 12) |
| 779 | #define MC13783_GPO4STBY (0x1 << 13) |
| 780 | #define MC13783_VIBPINCTRL (0x1 << 14) |
| 781 | #define MC13783_PWGT1SPIEN (0x1 << 15) |
| 782 | #define MC13783_PWGT2SPIEN (0x1 << 16) |
| 783 | |
| 784 | /* AUDIO_RX0 (36) */ |
| 785 | #define MC13783_VAUDIOON (0x1 << 0) |
| 786 | #define MC13783_BIASEN (0x1 << 1) |
| 787 | #define MC13783_BIASSPEED (0x1 << 2) |
| 788 | #define MC13783_ASPEN (0x1 << 3) |
| 789 | #define MC13783_ASPSEL (0x1 << 4) |
| 790 | #define MC13783_ALSPEN (0x1 << 5) |
| 791 | #define MC13783_ALSPREF (0x1 << 6) |
| 792 | #define MC13783_ALSPSEL (0x1 << 7) |
| 793 | #define MC13783_LSPLEN (0x1 << 8) |
| 794 | #define MC13783_AHSREN (0x1 << 9) |
| 795 | #define MC13783_AHSLEN (0x1 << 10) |
| 796 | #define MC13783_AHSSEL (0x1 << 11) |
| 797 | #define MC13783_HSPGDIS (0x1 << 12) |
| 798 | #define MC13783_HSDETEN (0x1 << 13) |
| 799 | #define MC13783_HSDETAUTOB (0x1 << 14) |
| 800 | #define MC13783_ARXOUTREN (0x1 << 15) |
| 801 | #define MC13783_ARXOUTLEN (0x1 << 16) |
| 802 | #define MC13783_ARXOUTSEL (0x1 << 17) |
| 803 | #define MC13783_CDCOUTEN (0x1 << 18) |
| 804 | #define MC13783_HSLDETEN (0x1 << 19) |
| 805 | #define MC13783_ADDCDC (0x1 << 21) |
| 806 | #define MC13783_ADDSTDC (0x1 << 22) |
| 807 | #define MC13783_ADDRXIN (0x1 << 23) |
| 808 | |
| 809 | /* AUDIO_RX1 (37) */ |
| 810 | #define MC13783_PGARXEN (0x1 << 0) |
| 811 | #define MC13783_PGARX (0xf << 1) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 812 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ |
| 813 | #define MC13783_PGARXw(x) (((x) << 1) & MC13783_PGARX) |
| 814 | #define MC13783_PGARXr(x) (((x) & MC13783_PGARX) >> 1) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 815 | #define MC13783_PGASTEN (0x1 << 5) |
| 816 | #define MC13783_PGAST (0xf << 6) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 817 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ |
| 818 | #define MC13783_PGASTw(x) (((x) << 6) & MC13783_PGAST) |
| 819 | #define MC13783_PGASTr(x) (((x) & MC13783_PGAST) >> 6) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 820 | #define MC13783_ARXINEN (0x1 << 10) |
| 821 | #define MC13783_ARXIN (0x1 << 11) |
| 822 | #define MC13783_PGARXIN (0xf << 12) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 823 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ |
| 824 | #define MC13783_PGARXINw(x) (((x) << 12) & MC13783_PGARXIN) |
| 825 | #define MC13783_PGARXINr(x) (((x) & MC13783_PGARXIN) >> 12) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 826 | #define MC13783_MONO (0x3 << 16) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 827 | #define MC13783_MONO_LR_INDEPENDENT (0x0 << 16) |
| 828 | #define MC13783_MONO_ST_OPPOSITE (0x1 << 16) |
| 829 | #define MC13783_MONO_ST_TO_MONO (0x2 << 16) |
| 830 | #define MC13783_MONO_MONO_OPPOSITE (0x3 << 16) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 831 | #define MC13783_BAL (0x7 << 18) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 832 | /* 000=-21dB...3dB steps...111=0dB: left or right */ |
| 833 | #define MC13783_BALw(x) (((x) << 18) & MC13783_BAL) |
| 834 | #define MC13783_BALr(x) (((x) & MC13783_BAL) >> 18) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 835 | #define MC13783_BALLR (0x1 << 21) |
| 836 | |
| 837 | /* AUDIO_TX (38) */ |
| 838 | #define MC13783_MC1BEN (0x1 << 0) |
| 839 | #define MC13783_MC2BEN (0x1 << 1) |
| 840 | #define MC13783_MC2BDETDBNC (0x1 << 2) |
| 841 | #define MC13783_MC2BDETEN (0x1 << 3) |
| 842 | #define MC13783_AMC1REN (0x1 << 5) |
| 843 | #define MC13783_AMC1RITOV (0x1 << 6) |
| 844 | #define MC13783_AMC1LEN (0x1 << 7) |
| 845 | #define MC13783_AMC1LITOV (0x1 << 8) |
| 846 | #define MC13783_AMC2EN (0x1 << 9) |
| 847 | #define MC13783_AMC2ITOV (0x1 << 10) |
| 848 | #define MC13783_ATXINEN (0x1 << 11) |
| 849 | #define MC13783_ATXOUTEN (0x1 << 12) |
| 850 | #define MC13783_RXINREC (0x1 << 13) |
| 851 | #define MC13783_PGATXR (0x1f << 14) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 852 | /* 00000=-8dB...01000=0dB...11111=+23dB */ |
| 853 | #define MC13783_PGATXRw(x) (((x) << 14) & MC13783_PGATXR) |
| 854 | #define MC13783_PGATXRr(x) (((x) & MC13783_PGATXR) >> 14) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 855 | #define MC13783_PGATXL (0x1f << 19) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 856 | /* 00000=-8dB...01000=0dB...11111=+23dB */ |
| 857 | #define MC13783_PGATXLw(x) (((x) << 19) & MC13783_PGATXL) |
| 858 | #define MC13783_PGATXLr(x) (((x) & MC13783_PGATXL) >> 19) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 859 | |
| 860 | /* SSI_NETWORK (39) */ |
| 861 | #define MC13783_CDCTXRXSLOT (0x3 << 2) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 862 | #define MC13783_CDCTXRXSLOT_TS0 (0x0 << 2) |
| 863 | #define MC13783_CDCTXRXSLOT_TS1 (0x1 << 2) |
| 864 | #define MC13783_CDCTXRXSLOT_TS2 (0x2 << 2) |
| 865 | #define MC13783_CDCTXRXSLOT_TS3 (0x3 << 2) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 866 | #define MC13783_CDCTXSECSLOT (0x3 << 4) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 867 | #define MC13783_CDCTXSECSLOT_TS0 (0x0 << 4) |
| 868 | #define MC13783_CDCTXSECSLOT_TS1 (0x1 << 4) |
| 869 | #define MC13783_CDCTXSECSLOT_TS2 (0x2 << 4) |
| 870 | #define MC13783_CDCTXSECSLOT_TS3 (0x3 << 4) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 871 | #define MC13783_CDCRXSECSLOT (0x3 << 6) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 872 | #define MC13783_CDCRXSECSLOT_TS0 (0x0 << 6) |
| 873 | #define MC13783_CDCRXSECSLOT_TS1 (0x1 << 6) |
| 874 | #define MC13783_CDCRXSECSLOT_TS2 (0x2 << 6) |
| 875 | #define MC13783_CDCRXSECSLOT_TS3 (0x3 << 6) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 876 | #define MC13783_CDCRXSECGAIN (0x3 << 8) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 877 | /* -inf, -0dB, -6dB, -12dB */ |
| 878 | #define MC13783_CDCRXSECGAINw(x) (((x) << 8) & MC13783_CDCRXSECGAIN) |
| 879 | #define MC13783_CDCRXSECGAINr(x) (((x) & MC13783_CDCRXSECGAIN) >> 8) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 880 | #define MC13783_CDCSUMGAIN (0x1 << 10) |
| 881 | #define MC13783_CDCFSDLY (0x1 << 11) |
| 882 | #define MC13783_STDCSLOTS (0x3 << 12) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 883 | #define MC13783_STDCSLOTS_8 (0x0 << 12) |
| 884 | #define MC13783_STDCSLOTS_LR6 (0x1 << 12) |
| 885 | #define MC13783_STDCSLOTS_LR2 (0x2 << 12) |
| 886 | #define MC13783_STDCSLOTS_LR (0x3 << 12) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 887 | #define MC13783_STDCRXSLOT (0x3 << 14) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 888 | #define MC13783_STDCRXSLOT_TS0_TS1 (0x0 << 14) |
| 889 | #define MC13783_STDCRXSLOT_TS2_TS3 (0x1 << 14) |
| 890 | #define MC13783_STDCRXSLOT_TS4_TS5 (0x2 << 14) |
| 891 | #define MC13783_STDCRXSLOT_TS6_TS7 (0x3 << 14) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 892 | #define MC13783_STDCRXSECSLOT (0x3 << 16) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 893 | #define MC13783_STDCRXSECSLOT_TS0_TS1 (0x0 << 16) |
| 894 | #define MC13783_STDCRXSECSLOT_TS2_TS3 (0x1 << 16) |
| 895 | #define MC13783_STDCRXSECSLOT_TS4_TS5 (0x2 << 16) |
| 896 | #define MC13783_STDCRXSECSLOT_TS6_TS7 (0x3 << 16) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 897 | #define MC13783_STDCRXSECGAIN (0x3 << 18) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 898 | /* -inf, -0dB, -6dB, -12dB */ |
| 899 | #define MC13783_STDCRXSECGAINw(x) (((x) << 8) & MC13783_STDCRXSECGAIN) |
| 900 | #define MC13783_STDCRXSECGAINr(x) (((x) & MC13783_STDCRXSECGAIN) >> 8) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 901 | #define MC13783_STDSUMGAIN (0x1 << 20) |
| 902 | |
| 903 | /* AUDIO_CODEC (40) */ |
| 904 | #define MC13783_CDCSSISEL (0x1 << 0) |
| 905 | #define MC13783_CDCCLKSEL (0x1 << 1) |
| 906 | #define MC13783_CDCSM (0x1 << 2) |
| 907 | #define MC13783_CDCBCLINV (0x1 << 3) |
| 908 | #define MC13783_CDCFSINV (0x1 << 4) |
| 909 | #define MC13783_CDCFS (0x3 << 5) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 910 | #define MC13783_CDCFS_NET (0x1 << 5) |
| 911 | #define MC13783_CDCFS_I2S (0x2 << 5) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 912 | #define MC13783_CDCCLK (0x7 << 7) |
| 913 | #define MC13783_CDCFS8K16K (0x1 << 10) |
| 914 | #define MC13783_CDCEN (0x1 << 11) |
| 915 | #define MC13783_CDCCLKEN (0x1 << 12) |
| 916 | #define MC13783_CDCTS (0x1 << 13) |
| 917 | #define MC13783_CDCDITH (0x1 << 14) |
| 918 | #define MC13783_CDCRESET (0x1 << 15) |
| 919 | #define MC13783_CDCBYP (0x1 << 16) |
| 920 | #define MC13783_CDCALM (0x1 << 17) |
| 921 | #define MC13783_CDCDLM (0x1 << 18) |
| 922 | #define MC13783_AUDIHPF (0x1 << 19) |
| 923 | #define MC13783_AUDOHPF (0x1 << 20) |
| 924 | |
| 925 | /* AUDIO_STEREO_DAC (41) */ |
| 926 | #define MC13783_STDCSSISEL (0x1 << 0) |
| 927 | #define MC13783_STDCCLKSEL (0x1 << 1) |
| 928 | #define MC13783_STDCSM (0x1 << 2) |
| 929 | #define MC13783_STDCBCLINV (0x1 << 3) |
| 930 | #define MC13783_STDCFSINV (0x1 << 4) |
| 931 | #define MC13783_STDCFS (0x3 << 5) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 932 | #define MC13783_STDCFS_NORMAL (0x0 << 5) |
| 933 | #define MC13783_STDCFS_NET (0x1 << 5) |
| 934 | #define MC13783_STDCFS_I2S (0x2 << 5) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 935 | #define MC13783_STDCCLK (0x7 << 7) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 936 | /* Master */ |
| 937 | #define MC13783_STDCCLK_13_0MHZ (0x0 << 7) |
| 938 | #define MC13783_STDCCLK_15_36MHZ (0x1 << 7) |
| 939 | #define MC13783_STDCCLK_16_8MHZ (0x2 << 7) |
| 940 | #define MC13783_STDCCLK_26_0MHZ (0x4 << 7) |
| 941 | #define MC13783_STDCCLK_12_0MHZ (0x5 << 7) |
| 942 | #define MC13783_STDCCLK_3_6864MHZ (0x6 << 7) |
| 943 | #define MC13783_STDCCLK_33_6MHZ (0x7 << 7) |
| 944 | /* Slave */ |
| 945 | #define MC13783_STDCCLK_CLIMCL (0x5 << 7) |
| 946 | #define MC13783_STDCCLK_FS (0x6 << 7) |
| 947 | #define MC13783_STDCCLK_BCL (0x7 << 7) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 948 | #define MC13783_STDCFSDLYB (0x1 << 10) |
| 949 | #define MC13783_STDCEN (0x1 << 11) |
| 950 | #define MC13783_STDCCLKEN (0x1 << 12) |
| 951 | #define MC13783_STDCRESET (0x1 << 15) |
| 952 | #define MC13783_SPDIF (0x1 << 16) |
| 953 | #define MC13783_SR (0xf << 17) |
| Michael Sevakis | 3c102ff | 2008-05-16 08:02:14 +0000 | [diff] [blame] | 954 | #define MC13783_SR_8000 (0x0 << 17) |
| 955 | #define MC13783_SR_11025 (0x1 << 17) |
| 956 | #define MC13783_SR_12000 (0x2 << 17) |
| 957 | #define MC13783_SR_16000 (0x3 << 17) |
| 958 | #define MC13783_SR_22050 (0x4 << 17) |
| 959 | #define MC13783_SR_24000 (0x5 << 17) |
| 960 | #define MC13783_SR_32000 (0x6 << 17) |
| 961 | #define MC13783_SR_44100 (0x7 << 17) |
| 962 | #define MC13783_SR_48000 (0x8 << 17) |
| 963 | #define MC13783_SR_64000 (0x9 << 17) |
| 964 | #define MC13783_SR_96000 (0xa << 17) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 965 | |
| 966 | /* ADC0 (43) */ |
| 967 | #define MC13783_LICELLCON (0x1 << 0) |
| 968 | #define MC13783_CHRGICON (0x1 << 1) |
| 969 | #define MC13783_BATICON (0x1 << 2) |
| 970 | #define MC13783_RTHEN (0x1 << 3) |
| 971 | #define MC13783_DTHEN (0x1 << 4) |
| 972 | #define MC13783_UIDEN (0x1 << 5) |
| 973 | #define MC13783_ADOUTEN (0x1 << 6) |
| 974 | #define MC13783_ADOUTPER (0x1 << 7) |
| 975 | #define MC13783_ADREFEN (0x1 << 10) |
| 976 | #define MC13783_ADREFMODE (0x1 << 11) |
| 977 | #define MC13783_TSMOD (0x7 << 12) |
| 978 | #define MC13783_TSMOD_INACTIVE (0x0 << 12) |
| 979 | #define MC13783_TSMOD_INTERRUPT (0x1 << 12) |
| 980 | #define MC13783_TSMOD_RESISTIVE (0x2 << 12) |
| 981 | #define MC13783_TSMOD_POSITION (0x3 << 12) |
| 982 | /* 0x4 - 0x7 = Inactive (same as 0x0) */ |
| 983 | #define MC13783_CHRGRAWDIV (0x1 << 15) |
| 984 | #define MC13783_ADINC1 (0x1 << 16) |
| 985 | #define MC13783_ADINC2 (0x1 << 17) |
| 986 | #define MC13783_WCOMP (0x1 << 18) |
| 987 | #define MC13783_ADCBIS0_ACCESS (0x1 << 23) |
| 988 | |
| 989 | /* ADC1 (44) */ |
| 990 | #define MC13783_ADEN (0x1 << 0) |
| 991 | #define MC13783_RAND (0x1 << 1) |
| 992 | #define MC13783_ADSEL (0x1 << 3) |
| 993 | #define MC13783_TRIGMASK (0x1 << 4) |
| 994 | #define MC13783_ADA1 (0x7 << 5) |
| 995 | #define MC13783_ADA1w(x) (((x) << 5) & MC13783_ADA1) |
| 996 | #define MC13783_ADA1r(x) (((x) & MC13783_ADA1) >> 5) |
| 997 | #define MC13783_ADA2 (0x7 << 8) |
| 998 | #define MC13783_ADA2w(x) (((x) << 8) & MC13783_ADA2) |
| 999 | #define MC13783_ADA2r(x) (((x) & MC13783_ADA2) >> 8) |
| 1000 | #define MC13783_ATO (0xff << 11) |
| 1001 | #define MC13783_ATOw(x) (((x) << 11) & MC13783_ATO) |
| 1002 | #define MC13783_ATOr(x) (((x) & MC13783_ATO) >> 11) |
| 1003 | #define MC13783_ATOX (0x1 << 19) |
| 1004 | #define MC13783_ASC (0x1 << 20) |
| 1005 | #define MC13783_ADTRIGIGN (0x1 << 21) |
| 1006 | #define MC13783_ADONESHOT (0x1 << 22) |
| 1007 | #define MC13783_ADCBIS1_ACCESS (0x1 << 23) |
| 1008 | |
| 1009 | /* ADC2 (45) */ |
| 1010 | #define MC13783_ADD1 (0x3ff << 2) |
| Michael Sevakis | 804bb8e | 2008-05-21 20:59:07 +0000 | [diff] [blame] | 1011 | #define MC13783_ADD1r(x) (((x) & MC13783_ADD1) >> 2) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 1012 | #define MC13783_ADD2 (0x3ff << 14) |
| Michael Sevakis | 804bb8e | 2008-05-21 20:59:07 +0000 | [diff] [blame] | 1013 | #define MC13783_ADD2r(x) (((x) & MC13783_ADD2) >> 14) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 1014 | |
| 1015 | /* ADC3 (46) */ |
| 1016 | #define MC13783_WHIGH (0x3f << 0) |
| 1017 | #define MC13783_WHIGHw(x) (((x) << 0) & MC13783_WHIGH) |
| 1018 | #define MC13783_WHIGHr(x) (((x) & MC13783_WHIGH) >> 0) |
| 1019 | #define MC13783_ICID (0x7 << 6) |
| 1020 | #define MC13783_ICIDr(x) (((x) & MC13783_ICID) >> 6) |
| 1021 | #define MC13783_WLOW (0x3f << 9) |
| 1022 | #define MC13783_WLOWw(x) (((x) << 9) & MC13783_WLOW) |
| 1023 | #define MC13783_WLOWr(x) (((x) & MC13783_WLOW) >> 9) |
| 1024 | #define MC13783_ADCBIS2_ACCESS (0x1 << 23) |
| 1025 | |
| 1026 | /* ADC4 (47) */ |
| 1027 | #define MC13783_ADCBIS1 (0x3ff << 2) |
| 1028 | #define MC13783_ADCBIS1r(x) (((x) & MC13783_ADCBIS1) >> 2) |
| 1029 | #define MC13783_ADCBIS2 (0x3ff << 14) |
| 1030 | #define MC13783_ADCBIS2r(x) (((x) & MC13783_ADCBIS2) >> 14) |
| 1031 | |
| 1032 | /* CHARGER (48) */ |
| 1033 | #define MC13783_VCHRG (0x7 << 0) |
| 1034 | #define MC13783_VCHRG_4_050V (0x0 << 0) |
| 1035 | #define MC13783_VCHRG_4_375V (0x1 << 0) |
| 1036 | #define MC13783_VCHRG_4_150V (0x2 << 0) |
| 1037 | #define MC13783_VCHRG_4_200V (0x3 << 0) |
| 1038 | #define MC13783_VCHRG_4_250V (0x4 << 0) |
| 1039 | #define MC13783_VCHRG_4_300V (0x5 << 0) |
| 1040 | #define MC13783_VCHRG_3_800V (0x6 << 0) |
| 1041 | #define MC13783_VCHRG_4_500V (0x7 << 0) |
| 1042 | #define MC13783_ICHRG (0xf << 3) /* Min Nom Max */ |
| 1043 | #define MC13783_ICHRG_0MA (0x0 << 3) /* 0 0 0 */ |
| 1044 | #define MC13783_ICHRG_70MA (0x1 << 3) /* 55 70 85 */ |
| 1045 | #define MC13783_ICHRG_177MA (0x2 << 3) /* 161 177 195 */ |
| 1046 | #define MC13783_ICHRG_266MA (0x3 << 3) /* 242 266 293 */ |
| 1047 | #define MC13783_ICHRG_355MA (0x4 << 3) /* 322 355 390 */ |
| 1048 | #define MC13783_ICHRG_443MA (0x5 << 3) /* 403 443 488 */ |
| 1049 | #define MC13783_ICHRG_532MA (0x6 << 3) /* 484 532 585 */ |
| 1050 | #define MC13783_ICHRG_621MA (0x7 << 3) /* 564 621 683 */ |
| 1051 | #define MC13783_ICHRG_709MA (0x8 << 3) /* 645 709 780 */ |
| 1052 | #define MC13783_ICHRG_798MA (0x9 << 3) /* 725 798 878 */ |
| 1053 | #define MC13783_ICHRG_886MA (0xa << 3) /* 806 886 975 */ |
| 1054 | #define MC13783_ICHRG_975MA (0xb << 3) /* 886 975 1073 */ |
| 1055 | #define MC13783_ICHRG_1064MA (0xc << 3) /* 967 1064 1170 */ |
| 1056 | #define MC13783_ICHRG_1152MA (0xd << 3) /* 1048 1152 1268 */ |
| 1057 | #define MC13783_ICHRG_1596MA (0xe << 3) /* 1450 1596 1755 */ |
| 1058 | #define MC13783_ICHRG_FULLY_ON (0xf << 3) /* Disallow HW FET turn on */ |
| 1059 | #define MC13783_ICHRGTR (0x7 << 7) /* Min Nom Max */ |
| 1060 | #define MC13783_ICHRGTR_0MA (0x0 << 7) /* 0 0 0 */ |
| 1061 | #define MC13783_ICHRGTR_9MA (0x1 << 7) /* 6 9 12 */ |
| 1062 | #define MC13783_ICHRGTR_20MA (0x2 << 7) /* 14 20 26 */ |
| 1063 | #define MC13783_ICHRGTR_36MA (0x3 << 7) /* 25 36 47 */ |
| 1064 | #define MC13783_ICHRGTR_42MA (0x4 << 7) /* 29 42 55 */ |
| 1065 | #define MC13783_ICHRGTR_50MA (0x5 << 7) /* 35 50 65 */ |
| 1066 | #define MC13783_ICHRGTR_59MA (0x6 << 7) /* 41 59 77 */ |
| 1067 | #define MC13783_ICHRGTR_68MA (0x7 << 7) /* 50 68 86 */ |
| 1068 | #define MC13783_FETOVRD (0x1 << 10) |
| 1069 | #define MC13783_FETCTRL (0x1 << 11) |
| 1070 | #define MC13783_RVRSMODE (0x1 << 13) |
| 1071 | #define MC13783_OVCTRL (0x3 << 15) |
| 1072 | #define MC13783_OVCTRL_5_83V (0x0 << 15) /* Not for separate! */ |
| 1073 | #define MC13783_OVCTRL_6_90V (0x1 << 15) |
| 1074 | #define MC13783_OVCTRL_9_80V (0x2 << 15) |
| 1075 | #define MC13783_OVCTRL_19_6V (0x3 << 15) |
| 1076 | #define MC13783_UCHEN (0x1 << 17) |
| 1077 | #define MC13783_CHRGLEDEN (0x1 << 18) |
| 1078 | #define MC13783_CHRGRAWPDEN (0x1 << 19) |
| 1079 | |
| 1080 | /* USB0 (49) */ |
| 1081 | #define MC13783_FSENB (0x1 << 0) |
| 1082 | #define MC13783_USBSUSPEND (0x1 << 1) |
| 1083 | #define MC13783_USBPU (0x1 << 2) |
| 1084 | #define MC13783_UDPPD (0x1 << 3) |
| 1085 | #define MC13783_UDMPD (0x1 << 4) |
| 1086 | #define MC13783_DP150KPU (0x1 << 5) |
| 1087 | #define MC13783_VBUS70KPDENB (0x1 << 6) |
| 1088 | #define MC13783_VBUSPULSETMR (0x7 << 7) |
| 1089 | #define MC13783_VBUSPULSETMR_NA (0x0 << 7) |
| 1090 | #define MC13783_VBUSPULSETMR_10MS (0x1 << 7) |
| 1091 | #define MC13783_VBUSPULSETMR_20MS (0x2 << 7) |
| 1092 | #define MC13783_VBUSPULSETMR_30MS (0x3 << 7) |
| 1093 | #define MC13783_VBUSPULSETMR_40MS (0x4 << 7) |
| 1094 | #define MC13783_VBUSPULSETMR_50MS (0x5 << 7) |
| 1095 | #define MC13783_VBUSPULSETMR_60MS (0x6 << 7) |
| 1096 | #define MC13783_VBUSPULSETMR_INF (0x7 << 7) |
| 1097 | #define MC13783_DLPSRP (0x1 << 10) |
| 1098 | #define MC13783_SE0CONN (0x1 << 11) |
| 1099 | #define MC13783_USBXCVREN (0x1 << 12) |
| 1100 | #define MC13783_CONMODE (0x7 << 14) |
| 1101 | #define MC13783_CONMODE_USB (0x0 << 14) |
| 1102 | #define MC13783_CONMODE_RS232 (0x1 << 14) /* and 0x2 */ |
| 1103 | #define MC13783_CONMODE_CEA_936_A (0x4 << 14) /* and 0x5...0x7 */ |
| 1104 | #define MC13783_DATSE0 (0x1 << 17) |
| 1105 | #define MC13783_BIDIR (0x1 << 18) |
| 1106 | #define MC13783_USBCNTRL (0x1 << 19) |
| 1107 | #define MC13783_IDPD (0x1 << 20) |
| 1108 | #define MC13783_IDPULSE (0x1 << 21) |
| 1109 | #define MC13783_IDPUCNTRL (0x1 << 22) |
| 1110 | #define MC13783_DMPULSE (0x1 << 23) |
| 1111 | |
| 1112 | /* CHARGER_USB1 (50) */ |
| 1113 | #define MC13783_USBIN (0x3 << 0) |
| 1114 | #define MC13783_USBIN_BOOST_VINBUS (0x0 << 0) |
| 1115 | #define MC13783_USBIN_VBUS (0x1 << 0) /* and 0x3 */ |
| 1116 | #define MC13783_USBIN_BP (0x2 << 0) /* VINVIB */ |
| 1117 | #define MC13783_VUSB (0x1 << 2) /* 0=3.2V, 1=3.3V */ |
| 1118 | #define MC13783_VUSBEN (0x1 << 3) |
| 1119 | #define MC13783_VBUSEN (0x1 << 5) |
| 1120 | #define MC13783_RSPOL (0x1 << 6) |
| 1121 | #define MC13783_RSTRI (0x1 << 7) |
| 1122 | #define MC13783_ID100KPU (0x1 << 8) |
| 1123 | |
| 1124 | /* LED_CONTROL0 (51) */ |
| 1125 | #define MC13783_LEDEN (0x1 << 0) |
| 1126 | #define MC13783_LEDMDRAMPUP (0x1 << 1) |
| 1127 | #define MC13783_LEDADRAMPUP (0x1 << 2) |
| 1128 | #define MC13783_LEDKDRAMPUP (0x1 << 3) |
| 1129 | #define MC13783_LEDMDRAMPDOWN (0x1 << 4) |
| 1130 | #define MC13783_LEDADRAMPDOWN (0x1 << 5) |
| 1131 | #define MC13783_LEDKDRAMPDOWN (0x1 << 6) |
| 1132 | #define MC13783_TRIODEMD (0x1 << 7) |
| 1133 | #define MC13783_TRIODEAD (0x1 << 8) |
| 1134 | #define MC13783_TRIODEKD (0x1 << 9) |
| 1135 | #define MC13783_BOOSTEN (0x1 << 10) |
| 1136 | #define MC13783_ABMODE (0x7 << 11) |
| Michael Sevakis | 2558365 | 2008-05-08 22:03:49 +0000 | [diff] [blame] | 1137 | #define MC13783_ABMODE_ADAPTIVE_BOOST_DISABLED (0x0 << 11) |
| 1138 | #define MC13783_ABMODE_MONCH_LEDMD1 (0x1 << 11) |
| 1139 | #define MC13783_ABMODE_MONCH_LEDMD12 (0x2 << 11) |
| 1140 | #define MC13783_ABMODE_MONCH_LEDMD123 (0x3 << 11) |
| 1141 | #define MC13783_ABMODE_MONCH_LEDMD1234 (0x4 << 11) |
| 1142 | #define MC13783_ABMODE_MONCH_LEDMD1234_LEADAD1 (0x5 << 11) |
| 1143 | #define MC13783_ABMODE_MONCH_LEDMD1234_LEADAD12 (0x6 << 11) |
| 1144 | #define MC13783_ABMODE_MONCH_LEDMD1_LEDAD_ACT (0x7 << 11) |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 1145 | #define MC13783_ABREF (0x3 << 14) |
| 1146 | #define MC13783_ABREF_200MV (0x0 << 14) |
| 1147 | #define MC13783_ABREF_400MV (0x1 << 14) |
| 1148 | #define MC13783_ABREF_600MV (0x2 << 14) |
| 1149 | #define MC13783_ABREF_800MV (0x3 << 14) |
| 1150 | #define MC13783_FLPATTRN (0xf << 17) |
| 1151 | #define MC13783_FLPATTRNw(x) (((x) << 17) & MC13783_FLPATTRN) |
| 1152 | #define MC13783_FLPATTRNr(x) (((x) & MC13783_FLPATTRN) >> 17) |
| 1153 | #define MC13783_FLBANK1 (0x1 << 21) |
| 1154 | #define MC13783_FLBANK2 (0x1 << 22) |
| 1155 | #define MC13783_FLBANK3 (0x1 << 23) |
| Michael Sevakis | a7af9e4 | 2008-04-12 16:56:45 +0000 | [diff] [blame] | 1156 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 1157 | /* LED_CONTROL1 (52) */ |
| 1158 | #define MC13783_LEDR1RAMPUP (0x1 << 0) |
| 1159 | #define MC13783_LEDG1RAMPUP (0x1 << 1) |
| 1160 | #define MC13783_LEDB1RAMPUP (0x1 << 2) |
| 1161 | #define MC13783_LEDR1RAMPDOWN (0x1 << 3) |
| 1162 | #define MC13783_LEDG1RAMPDOWN (0x1 << 4) |
| 1163 | #define MC13783_LEDB1RAMPDOWN (0x1 << 5) |
| 1164 | #define MC13783_LEDR2RAMPUP (0x1 << 6) |
| 1165 | #define MC13783_LEDG2RAMPUP (0x1 << 7) |
| 1166 | #define MC13783_LEDB2RAMPUP (0x1 << 8) |
| 1167 | #define MC13783_LEDR2RAMPDOWN (0x1 << 9) |
| 1168 | #define MC13783_LEDG2RAMPDOWN (0x1 << 10) |
| 1169 | #define MC13783_LEDB2RAMPDOWN (0x1 << 11) |
| 1170 | #define MC13783_LEDR3RAMPUP (0x1 << 12) |
| 1171 | #define MC13783_LEDG3RAMPUP (0x1 << 13) |
| 1172 | #define MC13783_LEDB3RAMPUP (0x1 << 14) |
| 1173 | #define MC13783_LEDR3RAMPDOWN (0x1 << 15) |
| 1174 | #define MC13783_LEDG3RAMPDOWN (0x1 << 16) |
| 1175 | #define MC13783_LEDB3RAMPDOWN (0x1 << 17) |
| 1176 | #define MC13783_TC1HALF (0x1 << 18) |
| 1177 | #define MC13783_SLEWLIMTC (0x1 << 23) |
| Michael Sevakis | 2558365 | 2008-05-08 22:03:49 +0000 | [diff] [blame] | 1178 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 1179 | /* LED_CONTROL2 (53) */ |
| 1180 | #define MC13783_LEDMD (0x7 << 0) |
| 1181 | #define MC13783_LEDMDw(x) (((x) << 0) & MC13783_LEDMD) |
| 1182 | #define MC13783_LEDMDr(x) (((x) & MC13783_LEDMD) >> 0) |
| 1183 | #define MC13783_LEDAD (0x7 << 3) |
| 1184 | #define MC13783_LEDADw(x) (((x) << 3) & MC13783_LEDAD) |
| 1185 | #define MC13783_LEDADr(x) (((x) & MC13783_LEDAD) >> 3) |
| 1186 | #define MC13783_LEDKP (0x7 << 6) |
| 1187 | #define MC13783_LEDKPw(x) (((x) << 6) & MC13783_LEDKP) |
| 1188 | #define MC13783_LEDKPr(x) (((x) & MC13783_LEDKP) >> 6) |
| 1189 | #define MC13783_LEDMDDC (0xf << 9) |
| 1190 | #define MC13783_LEDMDDCw(x) (((x) << 9) & MC13783_LEDMDDC) |
| 1191 | #define MC13783_LEDMDDCr(x) (((x) & MC13783_LEDMDDC) >> 9) |
| 1192 | #define MC13783_LEDADDC (0xf << 13) |
| 1193 | #define MC13783_LEDADDCw(x) (((x) << 13) & MC13783_LEDADDC) |
| 1194 | #define MC13783_LEDADDCr(x) (((x) & MC13783_LEDADDC) >> 13) |
| 1195 | #define MC13783_LEDKPDC (0xf << 17) |
| 1196 | #define MC13783_LEDKPDCw(x) (((x) << 17) & MC13783_LEDKPDC) |
| 1197 | #define MC13783_LEDKPDCr(x) (((x) & MC13783_LEDKPDC) >> 17) |
| 1198 | #define MC13783_BLPERIOD (0x1 << 21) |
| 1199 | #define MC13783_BLPERIODw(x) (((x) << 21) & MC13783_BLPERIOD) |
| 1200 | #define MC13783_BLPERIODr(x) (((x) & MC13783_BLPERIOD) >> 21) |
| 1201 | #define MC13783_SLEWLIMBL (0x1 << 23) |
| Michael Sevakis | 2558365 | 2008-05-08 22:03:49 +0000 | [diff] [blame] | 1202 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 1203 | /* LED_CONTROL3 (54) */ |
| 1204 | #define MC13783_LEDR1 (0x3 << 0) |
| 1205 | #define MC13783_LEDR1w(x) (((x) << 0) & MC13783_LEDR1) |
| 1206 | #define MC13783_LEDR1r(x) (((x) & MC13783_LEDR1) >> 0) |
| 1207 | #define MC13783_LEDG1 (0x3 << 2) |
| 1208 | #define MC13783_LEDG1w(x) (((x) << 2) & MC13783_LEDG1) |
| 1209 | #define MC13783_LEDG1r(x) (((x) & MC13783_LEDG1) >> 2) |
| 1210 | #define MC13783_LEDB1 (0x3 << 4) |
| 1211 | #define MC13783_LEDB1w(x) (((x) << 4) & MC13783_LEDB1) |
| 1212 | #define MC13783_LEDB1r(x) (((x) & MC13783_LEDB1) >> 4) |
| 1213 | #define MC13783_LEDR1DC (0x1f << 6) |
| 1214 | #define MC13783_LEDR1DCw(x) (((x) << 6) & MC13783_LEDR1DC) |
| 1215 | #define MC13783_LEDR1DCr(x) (((x) & MC13783_LEDR1DC) >> 6) |
| 1216 | #define MC13783_LEDG1DC (0x1f << 11) |
| 1217 | #define MC13783_LEDG1DCw(x) (((x) << 11) & MC13783_LEDG1DC) |
| 1218 | #define MC13783_LEDG1DCr(x) (((x) & MC13783_LEDG1DC) >> 11) |
| 1219 | #define MC13783_LEDB1DC (0x1f << 16) |
| 1220 | #define MC13783_LEDB1DCw(x) (((x) << 16) & MC13783_LEDB1DC) |
| 1221 | #define MC13783_LEDB1DCr(x) (((x) & MC13783_LEDB1DC) >> 16) |
| 1222 | #define MC13783_TC1PERIOD (0x3 << 21) |
| 1223 | #define MC13783_TC1PERIODw(x) (((x) << 21) & MC13783_TC1PERIOD) |
| 1224 | #define MC13783_TC1PERIODr(x) (((x) & MC13783_TC1PERIOD) >> 21) |
| 1225 | #define MC13783_TC1TRIODE (0x1 << 23) |
| Michael Sevakis | 2558365 | 2008-05-08 22:03:49 +0000 | [diff] [blame] | 1226 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 1227 | /* LED_CONTROL4 (55) */ |
| 1228 | #define MC13783_LEDR2 (0x3 << 0) |
| 1229 | #define MC13783_LEDR2w(x) (((x) << 0) & MC13783_LEDR2) |
| 1230 | #define MC13783_LEDR2r(x) (((x) & MC13783_LEDR2) >> 0) |
| 1231 | #define MC13783_LEDG2 (0x3 << 2) |
| 1232 | #define MC13783_LEDG2w(x) (((x) << 2) & MC13783_LEDG2) |
| 1233 | #define MC13783_LEDG2r(x) (((x) & MC13783_LEDG2) >> 2) |
| 1234 | #define MC13783_LEDB2 (0x3 << 4) |
| 1235 | #define MC13783_LEDB2w(x) (((x) << 4) & MC13783_LEDB2) |
| 1236 | #define MC13783_LEDB2r(x) (((x) & MC13783_LEDB2) >> 4) |
| 1237 | #define MC13783_LEDR2DC (0x1f << 6) |
| 1238 | #define MC13783_LEDR2DCw(x) (((x) << 6) & MC13783_LEDR2DC) |
| 1239 | #define MC13783_LEDR2DCr(x) (((x) & MC13783_LEDR2DC) >> 6) |
| 1240 | #define MC13783_LEDG2DC (0x1f << 11) |
| 1241 | #define MC13783_LEDG2DCw(x) (((x) << 11) & MC13783_LEDG2DC) |
| 1242 | #define MC13783_LEDG2DCr(x) (((x) & MC13783_LEDG2DC) >> 11) |
| 1243 | #define MC13783_LEDB2DC (0x1f << 16) |
| 1244 | #define MC13783_LEDB2DCw(x) (((x) << 16) & MC13783_LEDB2DC) |
| 1245 | #define MC13783_LEDB2DCr(x) (((x) & MC13783_LEDB2DC) >> 16) |
| 1246 | #define MC13783_TC2PERIOD (0x3 << 21) |
| 1247 | #define MC13783_TC2PERIODw(x) (((x) << 21) & MC13783_TC2PERIOD) |
| 1248 | #define MC13783_TC2PERIODr(x) (((x) & MC13783_TC2PERIOD) >> 21) |
| 1249 | #define MC13783_TC2TRIODE (0x1 << 23) |
| Michael Sevakis | 2558365 | 2008-05-08 22:03:49 +0000 | [diff] [blame] | 1250 | |
| Michael Sevakis | cda664b | 2008-05-16 06:21:11 +0000 | [diff] [blame] | 1251 | /* LED_CONTROL5 (56) */ |
| 1252 | #define MC13783_LEDR3 (0x3 << 0) |
| 1253 | #define MC13783_LEDR3w(x) (((x) << 0) & MC13783_LEDR3) |
| 1254 | #define MC13783_LEDR3r(x) (((x) & MC13783_LEDR3) >> 0) |
| 1255 | #define MC13783_LEDG3 (0x3 << 2) |
| 1256 | #define MC13783_LEDG3w(x) (((x) << 2) & MC13783_LEDG3) |
| 1257 | #define MC13783_LEDG3r(x) (((x) & MC13783_LEDG3) >> 2) |
| 1258 | #define MC13783_LEDB3 (0x3 << 4) |
| 1259 | #define MC13783_LEDB3w(x) (((x) << 4) & MC13783_LEDB3) |
| 1260 | #define MC13783_LEDB3r(x) (((x) & MC13783_LEDB3) >> 4) |
| 1261 | #define MC13783_LEDR3DC (0x1f << 6) |
| 1262 | #define MC13783_LEDR3DCw(x) (((x) << 6) & MC13783_LEDR3DC) |
| 1263 | #define MC13783_LEDR3DCr(x) (((x) & MC13783_LEDR3DC) >> 6) |
| 1264 | #define MC13783_LEDG3DC (0x1f << 11) |
| 1265 | #define MC13783_LEDG3DCw(x) (((x) << 11) & MC13783_LEDG3DC) |
| 1266 | #define MC13783_LEDG3DCr(x) (((x) & MC13783_LEDG3DC) >> 11) |
| 1267 | #define MC13783_LEDB3DC (0x1f << 16) |
| 1268 | #define MC13783_LEDB3DCw(x) (((x) << 16) & MC13783_LEDB3DC) |
| 1269 | #define MC13783_LEDB3DCr(x) (((x) & MC13783_LEDB3DC) >> 16) |
| 1270 | #define MC13783_TC3PERIOD (0x3 << 21) |
| 1271 | #define MC13783_TC3PERIODw(x) (((x) << 21) & MC13783_TC3PERIOD) |
| 1272 | #define MC13783_TC3PERIODr(x) (((x) & MC13783_TC3PERIOD) >> 21) |
| 1273 | #define MC13783_TC3TRIODE (0x1 << 23) |
| Michael Sevakis | b12c69b | 2008-04-13 20:03:08 +0000 | [diff] [blame] | 1274 | |
| Michael Sevakis | a9c20f5 | 2008-05-21 08:42:11 +0000 | [diff] [blame] | 1275 | /* For event enum values which are target-defined */ |
| 1276 | #include "mc13783-target.h" |
| 1277 | |
| Michael Sevakis | 0b1d7e7 | 2008-04-11 08:51:27 +0000 | [diff] [blame] | 1278 | void mc13783_init(void); |
| Michael Sevakis | 1ec3584 | 2008-05-10 18:32:34 +0000 | [diff] [blame] | 1279 | void mc13783_close(void); |
| Michael Sevakis | a7af9e4 | 2008-04-12 16:56:45 +0000 | [diff] [blame] | 1280 | uint32_t mc13783_set(unsigned address, uint32_t bits); |
| 1281 | uint32_t mc13783_clear(unsigned address, uint32_t bits); |
| Michael Sevakis | 0b1d7e7 | 2008-04-11 08:51:27 +0000 | [diff] [blame] | 1282 | int mc13783_write(unsigned address, uint32_t data); |
| Michael Sevakis | 2558365 | 2008-05-08 22:03:49 +0000 | [diff] [blame] | 1283 | uint32_t mc13783_write_masked(unsigned address, uint32_t data, uint32_t mask); |
| Michael Sevakis | 0b1d7e7 | 2008-04-11 08:51:27 +0000 | [diff] [blame] | 1284 | int mc13783_write_multiple(unsigned start, const uint32_t *buffer, int count); |
| Michael Sevakis | a7af9e4 | 2008-04-12 16:56:45 +0000 | [diff] [blame] | 1285 | int mc13783_write_regset(const unsigned char *regs, const uint32_t *data, int count); |
| Michael Sevakis | 0b1d7e7 | 2008-04-11 08:51:27 +0000 | [diff] [blame] | 1286 | uint32_t mc13783_read(unsigned address); |
| 1287 | int mc13783_read_multiple(unsigned start, uint32_t *buffer, int count); |
| Michael Sevakis | a7af9e4 | 2008-04-12 16:56:45 +0000 | [diff] [blame] | 1288 | int mc13783_read_regset(const unsigned char *regs, uint32_t *buffer, int count); |
| Michael Sevakis | a9c20f5 | 2008-05-21 08:42:11 +0000 | [diff] [blame] | 1289 | |
| 1290 | /* Statically-registered event enable/disable */ |
| 1291 | enum mc13783_event_sets |
| 1292 | { |
| 1293 | MC13783_EVENT_SET0 = 0, |
| 1294 | MC13783_EVENT_SET1 = 1, |
| 1295 | }; |
| 1296 | |
| 1297 | struct mc13783_event |
| 1298 | { |
| 1299 | enum mc13783_event_sets set : 8; |
| 1300 | uint32_t mask : 24; |
| 1301 | void (*callback)(void); |
| 1302 | }; |
| 1303 | |
| 1304 | struct mc13783_event_list |
| 1305 | { |
| 1306 | unsigned count; |
| 1307 | const struct mc13783_event *events; |
| 1308 | }; |
| 1309 | |
| 1310 | bool mc13783_enable_event(enum mc13783_event_ids event); |
| 1311 | void mc13783_disable_event(enum mc13783_event_ids event); |
| Michael Sevakis | 0b1d7e7 | 2008-04-11 08:51:27 +0000 | [diff] [blame] | 1312 | |
| 1313 | #endif /* _MC13783_H_ */ |