blob: 9724db2306180ab68a8331abfbc210adc5052457 [file] [log] [blame]
Björn Stenbergc521ed12002-09-03 09:44:08 +00001/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2002 Randy D. Wood
11 *
Daniel Stenberg2acc0ac2008-06-28 18:10:04 +000012 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
Björn Stenbergc521ed12002-09-03 09:44:08 +000016 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
Daniel Stenberg36355a52005-02-02 21:47:08 +000022#include "config.h"
Björn Stenbergc521ed12002-09-03 09:44:08 +000023#include "lcd.h"
Jens Arnold1aae0a02006-04-24 06:45:27 +000024#include "lcd-remote.h"
Michael Sevakis7914e902007-09-28 10:20:02 +000025#include "thread.h"
Björn Stenbergc521ed12002-09-03 09:44:08 +000026#include "kernel.h"
27#include "sprintf.h"
28#include "button.h"
29#include "file.h"
Linus Nielsen Feltzing8a237a82005-04-04 12:06:29 +000030#include "audio.h"
Björn Stenbergc521ed12002-09-03 09:44:08 +000031#include "system.h"
32#include "i2c.h"
Dave Chapman78d29f52008-03-26 23:35:34 +000033#include "adc.h"
Björn Stenbergc521ed12002-09-03 09:44:08 +000034#include "string.h"
Linus Nielsen Feltzing20d031f2003-05-09 16:01:21 +000035#include "buffer.h"
Bertrik Sikken2124a9f2008-05-03 07:17:44 +000036#include "rolo.h"
Björn Stenbergc521ed12002-09-03 09:44:08 +000037
Barry Wardell54c73a22007-06-04 13:48:21 +000038#ifdef MI4_FORMAT
39#include "crc32-mi4.h"
40#undef FIRMWARE_OFFSET_FILE_CRC
41#undef FIRMWARE_OFFSET_FILE_DATA
42#define FIRMWARE_OFFSET_FILE_CRC 0xC
43#define FIRMWARE_OFFSET_FILE_DATA 0x200
44#endif
45
Jens Arnold780f79e2006-11-10 20:26:01 +000046#if !defined(IRIVER_IFP7XX_SERIES) && \
Karl Kurbjun6c6a2ed2008-05-02 03:27:17 +000047 (CONFIG_CPU != PP5002)
Barry Wardell2f16d4f2006-12-19 11:33:53 +000048/* FIX: this doesn't work on iFP, 3rd Gen ipods */
Daniel Stenberg36355a52005-02-02 21:47:08 +000049
Björn Stenbergc521ed12002-09-03 09:44:08 +000050#define IRQ0_EDGE_TRIGGER 0x80
51
Daniel Ankersb8566362007-02-27 22:55:12 +000052#ifdef CPU_PP
53/* Handle the COP properly - it needs to jump to a function outside SDRAM while
54 * the new firmware is being loaded, and then jump to the start of SDRAM
55 * TODO: Use the mailboxes built into the PP processor for this
56 */
57
Michael Sevakis3e7d4f02007-09-29 06:56:21 +000058#if NUM_CORES > 1
Daniel Ankersb8566362007-02-27 22:55:12 +000059volatile unsigned char IDATA_ATTR cpu_message = 0;
60volatile unsigned char IDATA_ATTR cpu_reply = 0;
Michael Sevakis7914e902007-09-28 10:20:02 +000061extern int cop_idlestackbegin[];
Daniel Ankersb8566362007-02-27 22:55:12 +000062
63void rolo_restart_cop(void) ICODE_ATTR;
64void rolo_restart_cop(void)
65{
Michael Sevakis7914e902007-09-28 10:20:02 +000066 if (CURRENT_CORE == CPU)
67 {
68 /* There should be free thread slots aplenty */
69 create_thread(rolo_restart_cop, cop_idlestackbegin, IDLE_STACK_SIZE,
Michael Sevakisa9b2fb52007-10-16 01:25:17 +000070 0, "rolo COP" IF_PRIO(, PRIORITY_REALTIME)
71 IF_COP(, COP));
Michael Sevakis7914e902007-09-28 10:20:02 +000072 return;
73 }
74
Michael Sevakisfa5bd072008-06-03 05:19:32 +000075 COP_INT_DIS = -1;
Michael Sevakis7914e902007-09-28 10:20:02 +000076
Daniel Ankersb8566362007-02-27 22:55:12 +000077 /* Invalidate cache */
Michael Sevakisd95c3902007-04-13 20:55:48 +000078 invalidate_icache();
Daniel Ankersb8566362007-02-27 22:55:12 +000079
80 /* Disable cache */
Michael Sevakise760ba52007-09-30 10:53:31 +000081 CACHE_CTL = CACHE_CTL_DISABLE;
Daniel Ankersb8566362007-02-27 22:55:12 +000082
Daniel Ankersee072152007-03-04 23:53:38 +000083 /* Tell the main core that we're ready to reload */
Michael Sevakis7914e902007-09-28 10:20:02 +000084 cpu_reply = 1;
Daniel Ankersee072152007-03-04 23:53:38 +000085
Daniel Ankersb8566362007-02-27 22:55:12 +000086 /* Wait while RoLo loads the image into SDRAM */
87 /* TODO: Accept checksum failure gracefully */
Michael Sevakis7914e902007-09-28 10:20:02 +000088 while(cpu_message != 1);
Daniel Ankersb8566362007-02-27 22:55:12 +000089
Daniel Ankersee072152007-03-04 23:53:38 +000090 /* Acknowledge the CPU and then reload */
Michael Sevakis7914e902007-09-28 10:20:02 +000091 cpu_reply = 2;
Daniel Ankersb8566362007-02-27 22:55:12 +000092
93 asm volatile(
94 "mov r0, #0x10000000 \n"
95 "mov pc, r0 \n"
96 );
97}
Michael Sevakis3e7d4f02007-09-29 06:56:21 +000098#endif /* NUM_CORES > 1 */
99#endif /* CPU_PP */
Daniel Ankersb8566362007-02-27 22:55:12 +0000100
Jens Arnoldc76c5682004-08-16 23:37:23 +0000101static void rolo_error(const char *text)
Björn Stenbergc521ed12002-09-03 09:44:08 +0000102{
103 lcd_clear_display();
104 lcd_puts(0, 0, "ROLO error:");
105 lcd_puts_scroll(0, 1, text);
106 lcd_update();
107 button_get(true);
Linus Nielsen Feltzing20d031f2003-05-09 16:01:21 +0000108 button_get(true);
109 button_get(true);
Björn Stenbergc521ed12002-09-03 09:44:08 +0000110 lcd_stop_scroll();
111}
Jörg Hohensohncbbbcd12003-10-12 16:40:45 +0000112
Michael Sevakis6dd6ea72008-05-08 12:09:14 +0000113#if CONFIG_CPU == SH7034 || CONFIG_CPU == IMX31L
114/* these are in assembler file "descramble.S" for SH7034 */
Jens Arnoldc76c5682004-08-16 23:37:23 +0000115extern unsigned short descramble(const unsigned char* source,
116 unsigned char* dest, int length);
Michael Sevakis6dd6ea72008-05-08 12:09:14 +0000117/* this is in firmware/target/arm/imx31/rolo_restart.S for IMX31 */
Jens Arnoldc76c5682004-08-16 23:37:23 +0000118extern void rolo_restart(const unsigned char* source, unsigned char* dest,
119 int length);
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000120#else
Nils Wallménius4102ed52007-07-17 14:53:44 +0000121
122/* explicitly put this code in iram, ICODE_ATTR is defined to be null for some
123 targets that are low on iram, like the gigabeat F/X */
124void rolo_restart(const unsigned char* source, unsigned char* dest,
125 long length) __attribute__ ((section(".icode")));
126void rolo_restart(const unsigned char* source, unsigned char* dest,
127 long length)
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000128{
129 long i;
Jens Arnoldb7aaa642005-06-22 16:53:12 +0000130 unsigned char* localdest = dest;
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000131
Nils Wallménius76fa0f7e2007-07-16 19:26:07 +0000132 /* This is the equivalent of a call to memcpy() but this must be done from
133 iram to avoid overwriting itself and we don't want to depend on memcpy()
134 always being in iram */
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000135 for(i = 0;i < length;i++)
Jens Arnoldb7aaa642005-06-22 16:53:12 +0000136 *localdest++ = *source++;
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000137
Linus Nielsen Feltzing15db7f22006-07-13 21:11:20 +0000138#if defined(CPU_COLDFIRE)
Jens Arnoldb7aaa642005-06-22 16:53:12 +0000139 asm (
140 "movec.l %0,%%vbr \n"
141 "move.l (%0)+,%%sp \n"
142 "move.l (%0),%0 \n"
143 "jmp (%0) \n"
144 : : "a"(dest)
145 );
Jens Arnoldfe23dc82007-07-02 05:16:40 +0000146#elif defined(CPU_PP502x)
Michael Sevakis191320c2008-06-03 05:08:24 +0000147 CPU_INT_DIS = -1;
Daniel Ankersb8566362007-02-27 22:55:12 +0000148
Daniel Ankerscb51abb2006-12-10 15:20:26 +0000149 /* Flush cache */
Michael Sevakisd95c3902007-04-13 20:55:48 +0000150 flush_icache();
Daniel Ankerscb51abb2006-12-10 15:20:26 +0000151
Dave Chapmanffc0cab2006-07-23 14:30:10 +0000152 /* Disable cache */
Michael Sevakise760ba52007-09-30 10:53:31 +0000153 CACHE_CTL = CACHE_CTL_DISABLE;
Dave Chapmanffc0cab2006-07-23 14:30:10 +0000154
155 /* Reset the memory mapping registers to zero */
Michael Sevakise760ba52007-09-30 10:53:31 +0000156 {
157 volatile unsigned long *mmap_reg;
158 for (mmap_reg = &MMAP_FIRST; mmap_reg <= &MMAP_LAST; mmap_reg++)
159 *mmap_reg = 0;
160 }
Dave Chapmanffc0cab2006-07-23 14:30:10 +0000161
Michael Sevakis3e7d4f02007-09-29 06:56:21 +0000162#if NUM_CORES > 1
Michael Sevakis7914e902007-09-28 10:20:02 +0000163 /* Tell the COP it's safe to continue rebooting */
164 cpu_message = 1;
165
Daniel Ankersee072152007-03-04 23:53:38 +0000166 /* Wait for the COP to tell us it is rebooting */
Michael Sevakis7914e902007-09-28 10:20:02 +0000167 while(cpu_reply != 2);
Michael Sevakis3e7d4f02007-09-29 06:56:21 +0000168#endif
Karl Kurbjund3d0b262007-11-15 06:44:35 +0000169
Dave Chapmanffc0cab2006-07-23 14:30:10 +0000170 asm volatile(
171 "mov r0, #0x10000000 \n"
172 "mov pc, r0 \n"
173 );
Rob Purchased88c5662008-04-15 20:02:24 +0000174
Michael Sevakis6dd6ea72008-05-08 12:09:14 +0000175#elif defined(CPU_TCC780X) || (CONFIG_CPU == S3C2440)
Michael Sevakis7fee4862008-04-16 23:49:21 +0000176 /* Flush and invalidate caches */
177 invalidate_icache();
Rob Purchased88c5662008-04-15 20:02:24 +0000178
179 asm volatile(
180 "mov pc, %0 \n"
181 : : "r"(dest)
182 );
Dave Chapmand31a32c2005-11-11 17:51:35 +0000183#endif
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000184}
185#endif
186
187/* This is assigned in the linker control file */
188extern unsigned long loadaddress;
Jörg Hohensohncbbbcd12003-10-12 16:40:45 +0000189
Björn Stenbergc521ed12002-09-03 09:44:08 +0000190/***************************************************************************
191 *
192 * Name: rolo_load_app(char *filename,int scrambled)
193 * Filename must be a fully defined filename including the path and extension
194 *
195 ***************************************************************************/
Jens Arnoldc76c5682004-08-16 23:37:23 +0000196int rolo_load(const char* filename)
Björn Stenbergc521ed12002-09-03 09:44:08 +0000197{
Jörg Hohensohncbbbcd12003-10-12 16:40:45 +0000198 int fd;
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000199 long length;
Karl Kurbjunb7a4e102007-10-13 14:53:34 +0000200#if defined(CPU_COLDFIRE) || defined(CPU_ARM)
Barry Wardell54c73a22007-06-04 13:48:21 +0000201#if !defined(MI4_FORMAT)
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000202 int i;
Barry Wardell54c73a22007-06-04 13:48:21 +0000203#endif
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000204 unsigned long checksum,file_checksum;
205#else
206 long file_length;
Björn Stenbergc521ed12002-09-03 09:44:08 +0000207 unsigned short checksum,file_checksum;
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000208#endif
209 unsigned char* ramstart = (void*)&loadaddress;
Björn Stenbergc521ed12002-09-03 09:44:08 +0000210
211 lcd_clear_display();
212 lcd_puts(0, 0, "ROLO...");
213 lcd_puts(0, 1, "Loading");
214 lcd_update();
Jens Arnold1aae0a02006-04-24 06:45:27 +0000215#ifdef HAVE_REMOTE_LCD
216 lcd_remote_clear_display();
217 lcd_remote_puts(0, 0, "ROLO...");
218 lcd_remote_puts(0, 1, "Loading");
219 lcd_remote_update();
220#endif
Björn Stenbergc521ed12002-09-03 09:44:08 +0000221
Linus Nielsen Feltzing8a237a82005-04-04 12:06:29 +0000222 audio_stop();
Björn Stenbergc521ed12002-09-03 09:44:08 +0000223
224 fd = open(filename, O_RDONLY);
225 if(-1 == fd) {
226 rolo_error("File not found");
227 return -1;
228 }
229
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000230 length = filesize(fd) - FIRMWARE_OFFSET_FILE_DATA;
231
Rob Purchased88c5662008-04-15 20:02:24 +0000232#if defined(CPU_COLDFIRE) || defined(CPU_PP) || (CONFIG_CPU==DM320) \
Karl Kurbjun6c6a2ed2008-05-02 03:27:17 +0000233 || defined(CPU_TCC780X) || (CONFIG_CPU==IMX31L) || (CONFIG_CPU == S3C2440)
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000234 /* Read and save checksum */
235 lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
236 if (read(fd, &file_checksum, 4) != 4) {
237 rolo_error("Error Reading checksum");
238 return -1;
239 }
Dave Chapmanffc0cab2006-07-23 14:30:10 +0000240
Barry Wardell54c73a22007-06-04 13:48:21 +0000241#if !defined(MI4_FORMAT)
Dave Chapmanffc0cab2006-07-23 14:30:10 +0000242 /* Rockbox checksums are big-endian */
243 file_checksum = betoh32(file_checksum);
Barry Wardell54c73a22007-06-04 13:48:21 +0000244#endif
245
Michael Sevakis3e7d4f02007-09-29 06:56:21 +0000246#if defined(CPU_PP) && NUM_CORES > 1
Daniel Ankersee072152007-03-04 23:53:38 +0000247 lcd_puts(0, 2, "Waiting for coprocessor...");
248 lcd_update();
Michael Sevakis7914e902007-09-28 10:20:02 +0000249 rolo_restart_cop();
250 /* Wait for COP to be in safe code */
251 while(cpu_reply != 1);
Daniel Ankersee072152007-03-04 23:53:38 +0000252 lcd_puts(0, 2, " ");
253 lcd_update();
Daniel Ankersb8566362007-02-27 22:55:12 +0000254#endif
Dave Chapmanffc0cab2006-07-23 14:30:10 +0000255
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000256 lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
257
Linus Nielsen Feltzingd34865a2005-04-05 11:33:58 +0000258 if (read(fd, audiobuf, length) != length) {
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000259 rolo_error("Error Reading File");
260 return -1;
261 }
262
Barry Wardell54c73a22007-06-04 13:48:21 +0000263#ifdef MI4_FORMAT
264 /* Check CRC32 to see if we have a valid file */
265 chksum_crc32gentab();
266 checksum = chksum_crc32 (audiobuf, length);
267#else
Linus Nielsen Feltzingaa104222005-07-18 15:50:06 +0000268 checksum = MODEL_NUMBER;
Karl Kurbjunb7a4e102007-10-13 14:53:34 +0000269
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000270 for(i = 0;i < length;i++) {
Linus Nielsen Feltzingd34865a2005-04-05 11:33:58 +0000271 checksum += audiobuf[i];
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000272 }
Barry Wardell54c73a22007-06-04 13:48:21 +0000273#endif
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000274
275 /* Verify checksum against file header */
276 if (checksum != file_checksum) {
277 rolo_error("Checksum Error");
278 return -1;
279 }
280
Jens Arnold1aae0a02006-04-24 06:45:27 +0000281 lcd_puts(0, 1, "Executing");
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000282 lcd_update();
Jens Arnold1aae0a02006-04-24 06:45:27 +0000283#ifdef HAVE_REMOTE_LCD
284 lcd_remote_puts(0, 1, "Executing");
285 lcd_remote_update();
286#endif
Jens Arnolded3ff1b2008-03-17 23:47:38 +0000287 adc_close();
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000288
Michael Sevakisaf395f42008-03-26 01:50:41 +0000289#ifdef CPU_ARM
Michael Sevakis6dd6ea72008-05-08 12:09:14 +0000290 /* Should do these together since some ARM version should never have
291 * FIQ disabled and not IRQ (imx31 errata). */
292 disable_interrupt(IRQ_FIQ_STATUS);
293#else
294 /* Some targets have a higher disable level than HIGEST_IRQ_LEVEL */
Michael Sevakisaf395f42008-03-26 01:50:41 +0000295 set_irq_level(DISABLE_INTERRUPTS);
Michael Sevakis6dd6ea72008-05-08 12:09:14 +0000296#endif
Michael Sevakisaf395f42008-03-26 01:50:41 +0000297
Dave Chapman77372d12005-11-07 23:07:19 +0000298#elif CONFIG_CPU == SH7034
Björn Stenbergc521ed12002-09-03 09:44:08 +0000299 /* Read file length from header and compare to real file length */
Daniel Stenberg8f1d3c92003-01-22 18:47:35 +0000300 lseek(fd, FIRMWARE_OFFSET_FILE_LENGTH, SEEK_SET);
Björn Stenbergc521ed12002-09-03 09:44:08 +0000301 if(read(fd, &file_length, 4) != 4) {
302 rolo_error("Error Reading File Length");
303 return -1;
304 }
305 if (length != file_length) {
306 rolo_error("File length mismatch");
307 return -1;
308 }
Karl Kurbjunb7a4e102007-10-13 14:53:34 +0000309
Björn Stenbergc521ed12002-09-03 09:44:08 +0000310 /* Read and save checksum */
Daniel Stenberg8f1d3c92003-01-22 18:47:35 +0000311 lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
Björn Stenbergc521ed12002-09-03 09:44:08 +0000312 if (read(fd, &file_checksum, 2) != 2) {
313 rolo_error("Error Reading checksum");
314 return -1;
315 }
Daniel Stenberg8f1d3c92003-01-22 18:47:35 +0000316 lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
Björn Stenbergc521ed12002-09-03 09:44:08 +0000317
318 /* verify that file can be read and descrambled */
Linus Nielsen Feltzingd34865a2005-04-05 11:33:58 +0000319 if ((audiobuf + (2*length)+4) >= audiobufend) {
Björn Stenbergc521ed12002-09-03 09:44:08 +0000320 rolo_error("Not enough room to load file");
321 return -1;
322 }
323
Linus Nielsen Feltzingd34865a2005-04-05 11:33:58 +0000324 if (read(fd, &audiobuf[length], length) != (int)length) {
Björn Stenbergc521ed12002-09-03 09:44:08 +0000325 rolo_error("Error Reading File");
326 return -1;
327 }
328
Linus Nielsen Feltzing1c792602002-09-09 12:59:06 +0000329 lcd_puts(0, 1, "Descramble");
Björn Stenbergc521ed12002-09-03 09:44:08 +0000330 lcd_update();
331
Linus Nielsen Feltzingd34865a2005-04-05 11:33:58 +0000332 checksum = descramble(audiobuf + length, audiobuf, length);
Karl Kurbjunb7a4e102007-10-13 14:53:34 +0000333
Jörg Hohensohncbbbcd12003-10-12 16:40:45 +0000334 /* Verify checksum against file header */
Björn Stenbergc521ed12002-09-03 09:44:08 +0000335 if (checksum != file_checksum) {
336 rolo_error("Checksum Error");
337 return -1;
338 }
339
Linus Nielsen Feltzing1c792602002-09-09 12:59:06 +0000340 lcd_puts(0, 1, "Executing ");
Björn Stenbergc521ed12002-09-03 09:44:08 +0000341 lcd_update();
342
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000343 set_irq_level(HIGHEST_IRQ_LEVEL);
Karl Kurbjunb7a4e102007-10-13 14:53:34 +0000344
Björn Stenbergc521ed12002-09-03 09:44:08 +0000345 /* Calling these 2 initialization routines was necessary to get the
346 the origional Archos version of the firmware to load and execute. */
347 system_init(); /* Initialize system for restart */
348 i2c_init(); /* Init i2c bus - it seems like a good idea */
349 ICR = IRQ0_EDGE_TRIGGER; /* Make IRQ0 edge triggered */
Daniel Stenberg36355a52005-02-02 21:47:08 +0000350 TSTR = 0xE0; /* disable all timers */
Jens Arnoldab232fc2004-10-14 23:40:58 +0000351 /* model-specific de-init, needed when flashed */
352 /* Especially the Archos software is picky about this */
Daniel Stenberg36355a52005-02-02 21:47:08 +0000353#if defined(ARCHOS_RECORDER) || defined(ARCHOS_RECORDERV2) || \
354 defined(ARCHOS_FMRECORDER)
355 PAIOR = 0x0FA0;
Jörg Hohensohncbbbcd12003-10-12 16:40:45 +0000356#endif
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +0000357#endif
Linus Nielsen Feltzingd34865a2005-04-05 11:33:58 +0000358 rolo_restart(audiobuf, ramstart, length);
Björn Stenbergc521ed12002-09-03 09:44:08 +0000359
360 return 0; /* this is never reached */
Steve Bavinba58dd82008-04-15 15:41:13 +0000361 (void)checksum; (void)file_checksum;
Björn Stenbergc521ed12002-09-03 09:44:08 +0000362}
Jens Arnold780f79e2006-11-10 20:26:01 +0000363#else /* !defined(IRIVER_IFP7XX_SERIES) */
Daniel Stenberg36355a52005-02-02 21:47:08 +0000364int rolo_load(const char* filename)
365{
366 /* dummy */
Daniel Stenberge81fb192005-02-03 10:07:11 +0000367 (void)filename;
368 return 0;
Daniel Stenberg36355a52005-02-02 21:47:08 +0000369}
370
Jens Arnold780f79e2006-11-10 20:26:01 +0000371#endif /* !defined(IRIVER_IFP7XX_SERIES) */