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gerrit.rockbox.org / rockbox / 2acc0ac542d9186feee25bbe444c49cb59ca393e / . / firmware / target / coldfire / crt0.S
blob: dbf01a347ccb3ee26955a1e48c6bd41cc0583f32 [file] [log] [blame]
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2002 by Linus Nielsen Feltzing
11 *
Daniel Stenberg2acc0ac2008-06-28 18:10:04 +0000[diff] [blame^]12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#include "config.h"
22#include "cpu.h"
23
24 .section .init.text,"ax",@progbits
25
26 .global start
27start:
28
29 move.w #0x2700,%sr
30
31 move.l #vectors,%d0
32 movec.l %d0,%vbr
33
34 move.l #MBAR+1,%d0
35 movec.l %d0,%mbar
36
37 move.l #MBAR2+1,%d0
38 movec.l %d0,%mbar2
39
40 lea MBAR,%a0
41 lea MBAR2,%a1
42
43 clr.l (0x180,%a1) /* PLLCR = 0 */
44
45 /* 64K DMA-capable SRAM at 0x10000000
46 DMA is enabled and has priority in both banks
47 All types of accesses are allowed
48 (We might want to restrict that to save power) */
49 move.l #0x10000e01,%d0
50 movec.l %d0,%rambar1
51
52 /* 32K Non-DMA SRAM at 0x10010000
53 All types of accesses are allowed
54 (We might want to restrict that to save power) */
55 move.l #0x10010001,%d0
56 movec.l %d0,%rambar0
57
58 /* Chip select 0 - Flash ROM */
59 moveq.l #0x00,%d0 /* CSAR0 - Base = 0x00000000 */
60 move.l %d0,(0x080,%a0)
61 move.l #FLASH_SIZE-0x10000+1,%d0 /* CSMR0 - All access */
62 move.l %d0,(0x084,%a0)
63 move.l #0x00000180,%d0 /* CSCR0 - no wait states, 16 bits, no bursts */
64 move.l %d0,(0x088,%a0)
65
Jens Arnold769fcbd2008-03-12 20:35:42 +0000[diff] [blame]66#ifndef IAUDIO_M3
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]67 /* Chip select 1 - LCD controller */
68 move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */
69 move.l %d0,(0x08c,%a0)
70 moveq.l #0x1,%d0 /* CSMR1 - 64K */
71 move.l %d0,(0x090,%a0)
72 move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */
73 move.l %d0,(0x094,%a0)
Jens Arnold769fcbd2008-03-12 20:35:42 +0000[diff] [blame]74#endif
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]75
76 /* Chip select 2 - ATA controller */
77 move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */
78 move.l %d0,(0x098,%a0)
Jens Arnold81f76f22006-12-09 11:36:40 +0000[diff] [blame]79 moveq.l #0x1,%d0 /* CSMR2 - 64K */
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]80 move.l %d0,(0x09c,%a0)
81 move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */
Jens Arnold81f76f22006-12-09 11:36:40 +0000[diff] [blame]82 move.l %d0,(0x0a0,%a0) /* wait states are handled by the coldfire
83 * IDE interface logic. */
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]84
Jonathan Gordon1083de82007-02-18 01:17:06 +0000[diff] [blame]85#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]86 /* Chip select 3 - USBOTG controller */
87 move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */
88 move.l %d0,(0x0a4,%a0)
89 moveq.l #0x1,%d0 /* CSMR3 - 64K */
90 move.l %d0,(0x0a8,%a0)
91 move.l #0x00000180,%d0 /* CSCR3 - no wait states, 16 bits, no bursts */
92 move.l %d0,(0x0ac,%a0)
93#endif
94
95#ifdef BOOTLOADER
Miika Pekkarinen0ea4d312007-01-12 18:34:00 +0000[diff] [blame]96 /* Check if we have a Rockbox ROM image */
97 lea 0x00100000,%a2
98 move.l (%a2),%d0
99 move.l #FLASH_MAGIC,%d1
100 cmp.l %d0,%d1
101 beq.b .imagefound
102
103 /* Check for RAM image */
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]104 lea 0x00001000,%a2
105 move.l (%a2),%d0
Miika Pekkarinen0ea4d312007-01-12 18:34:00 +0000[diff] [blame]106 move.l #FLASH_MAGIC,%d1
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]107 cmp.l %d0,%d1
Miika Pekkarinen0ea4d312007-01-12 18:34:00 +0000[diff] [blame]108 beq.b .imagefound
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]109
Miika Pekkarinen0ea4d312007-01-12 18:34:00 +0000[diff] [blame]110 /* Not either ROM or RAM image was found, so original firmware
111 should be still present. */
112
113 /* Check if the cookie is present. */
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]114 lea 0x10017ffc,%a2
115 move.l (%a2),%d0
116 move.l #0xc0015a17,%d1
117 cmp.l %d0,%d1
118 bne.b .nocookie
Miika Pekkarinen0ea4d312007-01-12 18:34:00 +0000[diff] [blame]119
120 /* The cookie is not reset. This must mean that the boot loader
121 has crashed. Let's start the original firmware immediately. */
122 lea 0x10017ffc,%a2
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]123 clr.l (%a2)
124 jmp 8
125
126.nocookie:
127 /* Set the cookie */
128 move.l %d1,(%a2)
Miika Pekkarinen0ea4d312007-01-12 18:34:00 +0000[diff] [blame]129.imagefound:
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]130
131 /* Set up the DRAM controller. The refresh is based on the 11.2896MHz
132 clock (5.6448MHz bus frequency). We haven't yet started the PLL */
133#if MEM < 32
134 move.w #0x8004,%d0 /* DCR - Synchronous, 80 cycle refresh */
135#else
136 move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */
137#endif
138 move.w %d0,(0x100,%a0)
139
140 /* Note on 32Mbyte models:
141 We place the SDRAM on an 0x1000000 (16M) offset because
142 the 5249 BGA chip has a fault which disables the use of A24. The
143 suggested workaround by FreeScale is to offset the base address by
144 half the DRAM size and increase the mask to the double.
145 In our case this means that we set the base address 16M ahead and
146 use a 64M mask.
147 */
148#if MEM < 32
149 move.l #0x31002324,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up,
Jens Arnold41c1f172008-02-27 18:50:54 +0000[diff] [blame]150 CAS latency 2, Page mode, No refresh yet */
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]151 move.l %d0,(0x108,%a0)
152 move.l #0x00fc0001,%d0 /* Size: 16M */
153 move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */
154#else
155 move.l #0x31002524,%d0 /* DACR0 - Base 0x31000000, Banks on 23 and up,
Jens Arnold41c1f172008-02-27 18:50:54 +0000[diff] [blame]156 CAS latency 2, Page mode, No refresh yet */
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]157 move.l %d0,(0x108,%a0)
158 move.l #0x03fc0001,%d0 /* Size: 64M because of workaround above */
159 move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */
160#endif
161
162 /* Precharge */
163 moveq.l #8,%d0
164 or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a
165 Precharge command */
166 move.l #0xabcd1234,%d0
167 move.l %d0,0x31000000 /* Issue precharge command */
168
169 move.l #0x8000,%d0
170 or.l %d0,(0x108,%a0) /* Enable refresh */
171
172 /* Let it refresh */
173 move.l #500,%d0
174.delayloop:
175 subq.l #1,%d0
176 bne.b .delayloop
177
178 /* Mode Register init */
179 moveq.l #0x40,%d0 /* DACR0[IMRS] = 1, next access will set the
180 Mode Register */
181 or.l %d0,(0x108,%a0)
182
183 move.l #0xabcd1234,%d0
Jens Arnold41c1f172008-02-27 18:50:54 +0000[diff] [blame]184 move.l %d0,0x31000800 /* A11=1 means CASL=2 (connected to SDRAM A5). */
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]185
186 /* DACR0[IMRS] gets deactivated by the SDRAM controller */
Miika Pekkarinen0ea4d312007-01-12 18:34:00 +0000[diff] [blame]187
188 /* Check if we have a Rockbox ROM image. For RAM image only cookie is
189 not set at all. But we could support also RAM images loading. */
190 lea 0x00100000,%a2
191 move.l (%a2),%d0
192 move.l #FLASH_MAGIC,%d1
193 cmp.l %d0,%d1
194 bne.b .noromimage
195
196 /* Check again if the cookie is present. */
197 lea 0x10017ffc,%a2
198 move.l (%a2),%d0
199 move.l #0xc0015a17,%d1
200 cmp.l %d0,%d1
201 bne.b .nocookie2
202
203 /* We have found Rockbox in ROM!
204 Clear the cookie and load the ROM image */
205 lea 0x10017ffc,%a2
206 clr.l (%a2)
207 lea 0x00100028+4,%a2
208 move.l (%a2),%sp
209 lea 0x00100028+8,%a2
210 move.l (%a2),%d0
211 move.l %d0,%a2
212 jmp (%a2)
213
214.nocookie2:
215 /* Set the cookie */
216 move.l %d1,(%a2)
217.noromimage:
218
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]219#endif /* BOOTLOADER */
220
221 /* Invalicate cache */
222 move.l #0x01000000,%d0
223 movec.l %d0,%cacr
224
Jens Arnold3674af62007-10-17 20:45:13 +0000[diff] [blame]225 /* Enable cache, default=non-cacheable, no buffered writes */
226 move.l #0x80000000,%d0
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]227 movec.l %d0,%cacr
228
229 /* Cache enabled in SDRAM only, buffered writes enabled */
230 move.l #0x3103c020,%d0
231 movec.l %d0,%acr0
Jens Arnold3674af62007-10-17 20:45:13 +0000[diff] [blame]232 /* Buffered writes enabled for the LCD */
233 move.l #0xf000c060,%d0
Daniel Ankers41997d32006-08-31 19:45:05 +0000[diff] [blame]234 movec.l %d0,%acr1
235
236#ifndef BOOTLOADER
237 /* zero out .ibss */
238 lea _iedata,%a2
239 lea _iend,%a4
240 bra.b .iedatastart
241.iedataloop:
242 clr.l (%a2)+
243.iedatastart:
244 cmp.l %a2,%a4
245 bhi.b .iedataloop
246
247 /* copy the .iram section */
248 lea _iramcopy,%a2
249 lea _iramstart,%a3
250 lea _iramend,%a4
251 bra.b .iramstart
252.iramloop:
253 move.l (%a2)+,(%a3)+
254.iramstart:
255 cmp.l %a3,%a4
256 bhi.b .iramloop
257#endif /* !BOOTLOADER */
258
259#ifdef IRIVER_H300_SERIES
260 /* Set KEEP_ACT before doing the lengthy copy and zero-fill operations */
261 move.l #0x00080000,%d0
262 or.l %d0,(0xb4,%a1)
263 or.l %d0,(0xb8,%a1)
264 or.l %d0,(0xbc,%a1)
265#endif
266
267 /* zero out bss */
268 lea _edata,%a2
269 lea _end,%a4
270 bra.b .edatastart
271.edataloop:
272 clr.l (%a2)+
273.edatastart:
274 cmp.l %a2,%a4
275 bhi.b .edataloop
276
277 /* copy the .data section */
278 lea _datacopy,%a2
279 lea _datastart,%a3
280 cmp.l %a2,%a3
281 beq.b .nodatacopy /* Don't copy if src and dest are equal */
282 lea _dataend,%a4
283 bra.b .datastart
284.dataloop:
285 move.l (%a2)+,(%a3)+
286.datastart:
287 cmp.l %a3,%a4
288 bhi.b .dataloop
289.nodatacopy:
290
291 /* Munge the main stack */
292 lea stackbegin,%a2
293 lea stackend,%a4
294 move.l %a4,%sp
295 move.l #0xdeadbeef,%d0
296.mungeloop:
297 move.l %d0,(%a2)+
298 cmp.l %a2,%a4
299 bhi.b .mungeloop
300
301 jsr main
302.hoo:
303 bra.b .hoo
304
305 .section .resetvectors
306vectors:
307 .long stackend
308 .long start