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gerrit.rockbox.org / rockbox / 2acc0ac542d9186feee25bbe444c49cb59ca393e / . / firmware / target / coldfire / iaudio / m3 / system-m3.c
blob: 9c65619e1efb4a17c7eabe0131c12d0e1eeffb29 [file] [log] [blame]
Jens Arnold769fcbd2008-03-12 20:35:42 +0000[diff] [blame]1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 by Linus Nielsen Feltzing
11 *
Daniel Stenberg2acc0ac2008-06-28 18:10:04 +0000[diff] [blame^]12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
Jens Arnold769fcbd2008-03-12 20:35:42 +0000[diff] [blame]16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#include "config.h"
22#include "cpu.h"
23#include "kernel.h"
24#include "system.h"
25#include "power.h"
26#include "timer.h"
27
28/* Settings for all possible clock frequencies (with properly working timers)
29 * NOTE: Some 5249 chips don't like having PLLDIV set to 0. We must avoid that!
30 *
31 * xxx_REFRESH_TIMER below
32 * system.h, CPUFREQ_xxx_MULT |
33 * | |
34 * V V
35 * PLLCR & Rftim. IDECONFIG1/IDECONFIG2
36 * CPUCLK/Hz MULT ~0x70400000 16MB CSCR0 CS2Pre CS2Post CS2Wait
37 * -----------------------------------------------------------------
38 * 11289600 1 0x00800200 4 0x0180 1 1 0
39 * 22579200 2 0x0589e025 10 0x0180 1 1 0
40 * 33868800 3 0x0388e025 15 0x0180 1 1 0
41 * 45158400 4 0x0589e021 21 0x0580 1 1 0
42 * 56448000 5 0x0289e025 26 0x0580 2 1 0
43 * 67737600 6 0x0388e021 32 0x0980 2 1 0
44 * 79027200 7 0x038a6021 37 0x0980 2 1 0
45 * 90316800 8 0x038be021 43 0x0d80 2 1 0
46 * 101606400 9 0x01892025 48 0x0d80 2 1 0
47 * 112896000 10 0x0189e025 54 0x1180 3 1 0
48 * 124185600 11 0x018ae025 59 0x1180 3 1 1
49 */
50
51#define MAX_REFRESH_TIMER 59
52#define NORMAL_REFRESH_TIMER 21
53#define DEFAULT_REFRESH_TIMER 4
54
55#ifdef HAVE_ADJUSTABLE_CPU_FREQ
56void set_cpu_frequency (long) __attribute__ ((section (".icode")));
57void set_cpu_frequency(long frequency)
58#else
59void cf_set_cpu_frequency (long) __attribute__ ((section (".icode")));
60void cf_set_cpu_frequency(long frequency)
61#endif
62{
63 switch(frequency)
64 {
65 case CPUFREQ_MAX:
66 DCR = (0x8200 | DEFAULT_REFRESH_TIMER);
67 /* Refresh timer for bypass frequency */
68 PLLCR &= ~1; /* Bypass mode */
69 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
70 PLLCR = 0x018ae025 | (PLLCR & 0x70400000);
71 CSCR0 = 0x00001180; /* Flash: 4 wait states */
72 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
73 This may take up to 10ms! */
74 timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
75 DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
76 cpu_frequency = CPUFREQ_MAX;
77 IDECONFIG1 = 0x100000 | (1 << 13) | (3 << 10);
78 /* SBUFEN2 enable | CS2Post | CS2Pre */
79 IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
80 break;
81
82 case CPUFREQ_NORMAL:
83 DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
84 /* Refresh timer for bypass frequency */
85 PLLCR &= ~1; /* Bypass mode */
86 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
87 PLLCR = 0x0589e021 | (PLLCR & 0x70400000);
88 CSCR0 = 0x00000580; /* Flash: 1 wait state */
89 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
90 This may take up to 10ms! */
91 timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
92 DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
93 cpu_frequency = CPUFREQ_NORMAL;
94 IDECONFIG1 = 0x100000 | (1 << 13) | (1 << 10);
95 /* BUFEN2 enable | CS2Post | CS2Pre */
96 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
97 break;
98
99 default:
100 DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
101 /* Refresh timer for bypass frequency */
102 PLLCR &= ~1; /* Bypass mode */
103 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
104 /* Power down PLL, but keep CRSEL and CLSEL */
105 PLLCR = 0x00800200 | (PLLCR & 0x70400000);
106 CSCR0 = 0x00000180; /* Flash: 0 wait states */
107 DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
108 cpu_frequency = CPUFREQ_DEFAULT;
109 IDECONFIG1 = 0x100000 | (1 << 13) | (1 << 10);
110 /* BUFEN2 enable | CS2Post | CS2Pre */
111 IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
112 break;
113 }
114}