Blame - firmware/system.c - rockbox

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Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	1	/***************************************************************************
				2	* __________ __ ___.
				3	* Open \______ \ ____ ____ \| \| _\_ \|__ _______ ___
				4	* Source \| _// _ \_/ ___\\| \|/ /\| __ \ / _ \ \/ /
				5	* Jukebox \| \| ( <_> ) \___\| < \| \_\ ( <_> > < <
				6	* Firmware \|____\|_ /\____/ \___ >__\|_ \\|___ /\____/__/\_ \
				7	* \/ \/ \/ \/ \/
				8	* $Id$
				9	*
				10	* Copyright (C) 2002 by Alan Korr
				11	*
				12	* All files in this archive are subject to the GNU General Public License.
				13	* See the file COPYING in the source tree root for full license agreement.
				14	*
				15	* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
				16	* KIND, either express or implied.
				17	*
				18	****************************************************************************/
Björn Stenberg	6eb7717	2002-05-24 15:22:33 +0000	[diff] [blame]	19	#include <stdio.h>
Daniel Stenberg	439b187	2002-04-16 14:02:26 +0000	[diff] [blame]	20	#include "config.h"
				21
Eric Linenberg	038df5c	2002-09-16 03:18:49 +0000	[diff] [blame]	22	#include "lcd.h"
				23	#include "font.h"
Linus Nielsen Feltzing	fe6b82f	2002-04-28 21:40:24 +0000	[diff] [blame]	24	#include "led.h"
Linus Nielsen Feltzing	40c1c22	2002-04-29 14:23:21 +0000	[diff] [blame]	25	#include "system.h"
Björn Stenberg	9bcbe3f	2003-06-29 15:09:01 +0000	[diff] [blame]	26	#include "rolo.h"
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	27
				28	#define default_interrupt(name,number) \
				29	extern __attribute__((weak,alias("UIE" #number))) void name (void); void UIE##number (void)
				30	#define reserve_interrupt(number) \
				31	void UIE##number (void)
				32
				33	extern void reset_pc (void);
				34	extern void reset_sp (void);
				35
Björn Stenberg	2dd18d3	2002-05-28 13:38:42 +0000	[diff] [blame]	36	static const char* irqname[] = {
				37	"", "", "", "", "IllInstr", "", "IllSltIn","","",
				38	"CPUAdrEr", "DMAAdrEr", "NMI", "UserBrk",
				39	"","","","","","","","","","","","","","","","","","","",
				40	"Trap32","Trap33","Trap34","Trap35","Trap36","Trap37","Trap38","Trap39",
				41	"Trap40","Trap41","Trap42","Trap43","Trap44","Trap45","Trap46","Trap47",
				42	"Trap48","Trap49","Trap50","Trap51","Trap52","Trap53","Trap54","Trap55",
				43	"Trap56","Trap57","Trap58","Trap59","Trap60","Trap61","Trap62","Trap63",
				44	"Irq0","Irq1","Irq2","Irq3","Irq4","Irq5","Irq6","Irq7",
				45	"Dma0","","Dma1","","Dma2","","Dma3","",
				46	"IMIA0","IMIB0","OVI0","", "IMIA1","IMIB1","OVI1","",
				47	"IMIA2","IMIB2","OVI2","", "IMIA3","IMIB3","OVI3","",
				48	"IMIA4","IMIB4","OVI4","",
				49	"Ser0Err","Ser0Rx","Ser0Tx","Ser0TE",
				50	"Ser1Err","Ser1Rx","Ser1Tx","Ser1TE",
				51	"ParityEr","A/D conv","","","Watchdog","DRAMRefr"
				52	};
				53
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	54	reserve_interrupt ( 0);
				55	reserve_interrupt ( 1);
				56	reserve_interrupt ( 2);
				57	reserve_interrupt ( 3);
				58	default_interrupt (GII, 4);
				59	reserve_interrupt ( 5);
				60	default_interrupt (ISI, 6);
				61	reserve_interrupt ( 7);
				62	reserve_interrupt ( 8);
				63	default_interrupt (CPUAE, 9);
				64	default_interrupt (DMAAE, 10);
				65	default_interrupt (NMI, 11);
				66	default_interrupt (UB, 12);
				67	reserve_interrupt ( 13);
				68	reserve_interrupt ( 14);
				69	reserve_interrupt ( 15);
Björn Stenberg	df194b0	2003-02-23 19:02:31 +0000	[diff] [blame]	70	reserve_interrupt ( 16); /* TCB #0 */
				71	reserve_interrupt ( 17); /* TCB #1 */
				72	reserve_interrupt ( 18); /* TCB #2 */
				73	reserve_interrupt ( 19); /* TCB #3 */
				74	reserve_interrupt ( 20); /* TCB #4 */
				75	reserve_interrupt ( 21); /* TCB #5 */
				76	reserve_interrupt ( 22); /* TCB #6 */
				77	reserve_interrupt ( 23); /* TCB #7 */
				78	reserve_interrupt ( 24); /* TCB #8 */
				79	reserve_interrupt ( 25); /* TCB #9 */
				80	reserve_interrupt ( 26); /* TCB #10 */
				81	reserve_interrupt ( 27); /* TCB #11 */
				82	reserve_interrupt ( 28); /* TCB #12 */
				83	reserve_interrupt ( 29); /* TCB #13 */
				84	reserve_interrupt ( 30); /* TCB #14 */
				85	reserve_interrupt ( 31); /* TCB #15 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	86	default_interrupt (TRAPA32, 32);
				87	default_interrupt (TRAPA33, 33);
				88	default_interrupt (TRAPA34, 34);
				89	default_interrupt (TRAPA35, 35);
				90	default_interrupt (TRAPA36, 36);
				91	default_interrupt (TRAPA37, 37);
				92	default_interrupt (TRAPA38, 38);
				93	default_interrupt (TRAPA39, 39);
				94	default_interrupt (TRAPA40, 40);
				95	default_interrupt (TRAPA41, 41);
				96	default_interrupt (TRAPA42, 42);
				97	default_interrupt (TRAPA43, 43);
				98	default_interrupt (TRAPA44, 44);
				99	default_interrupt (TRAPA45, 45);
				100	default_interrupt (TRAPA46, 46);
				101	default_interrupt (TRAPA47, 47);
				102	default_interrupt (TRAPA48, 48);
				103	default_interrupt (TRAPA49, 49);
				104	default_interrupt (TRAPA50, 50);
				105	default_interrupt (TRAPA51, 51);
				106	default_interrupt (TRAPA52, 52);
				107	default_interrupt (TRAPA53, 53);
				108	default_interrupt (TRAPA54, 54);
				109	default_interrupt (TRAPA55, 55);
				110	default_interrupt (TRAPA56, 56);
				111	default_interrupt (TRAPA57, 57);
				112	default_interrupt (TRAPA58, 58);
				113	default_interrupt (TRAPA59, 59);
				114	default_interrupt (TRAPA60, 60);
				115	default_interrupt (TRAPA61, 61);
				116	default_interrupt (TRAPA62, 62);
				117	default_interrupt (TRAPA63, 63);
				118	default_interrupt (IRQ0, 64);
				119	default_interrupt (IRQ1, 65);
				120	default_interrupt (IRQ2, 66);
				121	default_interrupt (IRQ3, 67);
				122	default_interrupt (IRQ4, 68);
				123	default_interrupt (IRQ5, 69);
				124	default_interrupt (IRQ6, 70);
				125	default_interrupt (IRQ7, 71);
				126	default_interrupt (DEI0, 72);
				127	reserve_interrupt ( 73);
				128	default_interrupt (DEI1, 74);
				129	reserve_interrupt ( 75);
				130	default_interrupt (DEI2, 76);
				131	reserve_interrupt ( 77);
				132	default_interrupt (DEI3, 78);
				133	reserve_interrupt ( 79);
				134	default_interrupt (IMIA0, 80);
				135	default_interrupt (IMIB0, 81);
				136	default_interrupt (OVI0, 82);
				137	reserve_interrupt ( 83);
				138	default_interrupt (IMIA1, 84);
				139	default_interrupt (IMIB1, 85);
				140	default_interrupt (OVI1, 86);
				141	reserve_interrupt ( 87);
				142	default_interrupt (IMIA2, 88);
				143	default_interrupt (IMIB2, 89);
				144	default_interrupt (OVI2, 90);
				145	reserve_interrupt ( 91);
				146	default_interrupt (IMIA3, 92);
				147	default_interrupt (IMIB3, 93);
				148	default_interrupt (OVI3, 94);
				149	reserve_interrupt ( 95);
				150	default_interrupt (IMIA4, 96);
				151	default_interrupt (IMIB4, 97);
				152	default_interrupt (OVI4, 98);
				153	reserve_interrupt ( 99);
				154	default_interrupt (REI0, 100);
				155	default_interrupt (RXI0, 101);
				156	default_interrupt (TXI0, 102);
				157	default_interrupt (TEI0, 103);
				158	default_interrupt (REI1, 104);
				159	default_interrupt (RXI1, 105);
				160	default_interrupt (TXI1, 106);
				161	default_interrupt (TEI1, 107);
				162	reserve_interrupt ( 108);
				163	default_interrupt (ADITI, 109);
				164
Linus Nielsen Feltzing	db82218	2002-04-24 21:55:32 +0000	[diff] [blame]	165	/* reset vectors are handled in crt0.S */
				166	void (*vbr[]) (void) __attribute__ ((section (".vectors"))) =
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	167	{
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	168	/* 4 General Illegal Instruction */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	169
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	170	GII,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	171
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	172	/* 5 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	173
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	174	UIE5,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	175
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	176	/* 6 Illegal Slot Instruction */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	177
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	178	ISI,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	179
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	180	/* 7-8 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	181
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	182	UIE7,UIE8,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	183
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	184	/* 9 CPU Address Error */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	185
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	186	CPUAE,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	187
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	188	/* 10 DMA Address Error */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	189
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	190	DMAAE,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	191
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	192	/* 11 NMI */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	193
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	194	NMI,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	195
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	196	/* 12 User Break */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	197
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	198	UB,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	199
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	200	/* 13-31 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	201
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	202	UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	203
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	204	/* 32-63 TRAPA #20...#3F */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	205
				206	TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63,
				207
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	208	/* 64-71 IRQ0-7 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	209
				210	IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,
				211
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	212	/* 72 DMAC0 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	213
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	214	DEI0,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	215
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	216	/* 73 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	217
				218	UIE73,
				219
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	220	/* 74 DMAC1 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	221
				222	DEI1,
				223
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	224	/* 75 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	225
				226	UIE75,
				227
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	228	/* 76 DMAC2 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	229
				230	DEI2,
				231
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	232	/* 77 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	233
				234	UIE77,
				235
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	236	/* 78 DMAC3 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	237
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	238	DEI3,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	239
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	240	/* 79 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	241
				242	UIE79,
				243
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	244	/* 80-82 ITU0 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	245
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	246	IMIA0,IMIB0,OVI0,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	247
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	248	/* 83 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	249
				250	UIE83,
				251
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	252	/* 84-86 ITU1 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	253
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	254	IMIA1,IMIB1,OVI1,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	255
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	256	/* 87 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	257
				258	UIE87,
				259
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	260	/* 88-90 ITU2 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	261
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	262	IMIA2,IMIB2,OVI2,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	263
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	264	/* 91 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	265
				266	UIE91,
				267
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	268	/* 92-94 ITU3 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	269
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	270	IMIA3,IMIB3,OVI3,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	271
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	272	/* 95 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	273
				274	UIE95,
				275
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	276	/* 96-98 ITU4 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	277
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	278	IMIA4,IMIB4,OVI4,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	279
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	280	/* 99 Reserved */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	281
				282	UIE99,
				283
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	284	/* 100-103 SCI0 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	285
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	286	REI0,RXI0,TXI0,TEI0,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	287
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	288	/* 104-107 SCI1 */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	289
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	290	REI1,RXI1,TXI1,TEI1,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	291
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	292	/* 108 Parity Control Unit */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	293
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	294	UIE108,
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	295
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	296	/* 109 AD Converter */
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	297
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	298	ADITI
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	299
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	300	};
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	301
				302
				303	void system_reboot (void)
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	304	{
Jörg Hohensohn	81e309d	2004-03-13 16:45:18 +0000	[diff] [blame]	305	set_irq_level(HIGHEST_IRQ_LEVEL);
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	306
				307	asm volatile ("ldc\t%0,vbr" : : "r"(0));
				308
Jörg Hohensohn	782e237	2003-07-17 20:19:01 +0000	[diff] [blame]	309	PACR2 \|= 0x4000; /* for coldstart detection */
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	310	IPRA = 0;
				311	IPRB = 0;
				312	IPRC = 0;
				313	IPRD = 0;
				314	IPRE = 0;
				315	ICR = 0;
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	316
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	317	asm volatile ("jmp @%0; mov.l @%1,r15" : :
Linus Nielsen Feltzing	72315c2	2002-06-26 22:39:22 +0000	[diff] [blame]	318	"r"((int)0),"r"(4));
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	319	}
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	320
				321	void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	322	{
Björn Stenberg	6eb7717	2002-05-24 15:22:33 +0000	[diff] [blame]	323	bool state = true;
Linus Nielsen Feltzing	db82218	2002-04-24 21:55:32 +0000	[diff] [blame]	324	unsigned int n;
Björn Stenberg	6eb7717	2002-05-24 15:22:33 +0000	[diff] [blame]	325	char str[32];
Linus Nielsen Feltzing	db82218	2002-04-24 21:55:32 +0000	[diff] [blame]	326
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	327	asm volatile ("sts\tpr,%0" : "=r"(n));
Björn Stenberg	9bcbe3f	2003-06-29 15:09:01 +0000	[diff] [blame]	328
Felix Arends	b38c2d9	2002-06-24 11:35:13 +0000	[diff] [blame]	329	/* clear screen */
				330	lcd_clear_display ();
Daniel Stenberg	fba7a41	2002-09-16 06:51:43 +0000	[diff] [blame]	331	#ifdef HAVE_LCD_BITMAP
Eric Linenberg	038df5c	2002-09-16 03:18:49 +0000	[diff] [blame]	332	lcd_setfont(FONT_SYSFIXED);
Daniel Stenberg	fba7a41	2002-09-16 06:51:43 +0000	[diff] [blame]	333	#endif
Felix Arends	b38c2d9	2002-06-24 11:35:13 +0000	[diff] [blame]	334	/* output exception */
Björn Stenberg	df194b0	2003-02-23 19:02:31 +0000	[diff] [blame]	335	n = (n - (unsigned)UIE0 - 4)>>2; /* get exception or interrupt number */
Björn Stenberg	2dd18d3	2002-05-28 13:38:42 +0000	[diff] [blame]	336	snprintf(str,sizeof(str),"I%02x:%s",n,irqname[n]);
Björn Stenberg	6eb7717	2002-05-24 15:22:33 +0000	[diff] [blame]	337	lcd_puts(0,0,str);
				338	snprintf(str,sizeof(str),"at %08x",pc);
				339	lcd_puts(0,1,str);
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	340
Felix Arends	b38c2d9	2002-06-24 11:35:13 +0000	[diff] [blame]	341	#ifdef HAVE_LCD_BITMAP
				342	lcd_update ();
				343	#endif
				344
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	345	while (1)
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	346	{
Björn Stenberg	6eb7717	2002-05-24 15:22:33 +0000	[diff] [blame]	347	volatile int i;
Linus Nielsen Feltzing	fe6b82f	2002-04-28 21:40:24 +0000	[diff] [blame]	348	led (state);
Björn Stenberg	2382044	2002-05-13 12:29:34 +0000	[diff] [blame]	349	state = state?false:true;
Linus Nielsen Feltzing	40c1c22	2002-04-29 14:23:21 +0000	[diff] [blame]	350
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	351	for (i = 0; i < 240000; ++i);
Björn Stenberg	9bcbe3f	2003-06-29 15:09:01 +0000	[diff] [blame]	352
				353	/* try to restart firmware if ON is pressed */
				354	#ifdef HAVE_LCD_CHARCELLS
				355	if (!(PADR & 0x20))
				356	rolo_load("/archos.mod");
				357	#else
				358	if (!(PBDR & PBDR_BTN_ON))
				359	rolo_load("/ajbrec.ajz");
				360	#endif
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	361	}
				362	}
Björn Stenberg	d9eb5c7	2002-03-28 15:09:10 +0000	[diff] [blame]	363
				364	asm (
Björn Stenberg	191f4d2	2002-04-20 13:25:58 +0000	[diff] [blame]	365	"_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				366	"_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				367	"_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				368	"_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				369	"_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				370	"_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				371	"_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				372	"_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				373	"_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				374	"_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				375	"_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				376	"_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				377	"_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				378	"_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				379	"_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				380	"_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				381	"_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				382	"_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				383	"_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				384	"_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				385	"_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				386	"_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				387	"_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				388	"_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				389	"_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				390	"_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				391	"_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				392	"_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				393	"_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				394	"_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				395	"_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				396	"_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				397	"_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				398	"_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				399	"_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				400	"_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				401	"_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				402	"_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				403	"_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				404	"_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				405	"_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				406	"_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				407	"_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				408	"_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				409	"_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				410	"_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				411	"_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				412	"_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				413	"_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				414	"_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				415	"_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				416	"_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				417	"_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				418	"_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				419	"_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				420	"_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				421	"_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				422	"_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				423	"_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				424	"_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				425	"_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				426	"_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				427	"_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				428	"_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				429	"_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				430	"_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				431	"_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				432	"_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				433	"_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				434	"_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				435	"_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				436	"_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				437	"_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				438	"_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				439	"_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				440	"_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				441	"_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				442	"_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				443	"_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				444	"_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				445	"_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				446	"_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				447	"_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				448	"_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				449	"_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				450	"_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				451	"_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				452	"_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				453	"_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				454	"_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				455	"_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				456	"_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				457	"_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				458	"_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				459	"_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				460	"_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				461	"_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				462	"_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				463	"_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				464	"_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				465	"_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				466	"_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				467	"_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				468	"_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				469	"_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				470	"_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				471	"_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				472	"_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				473	"_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
				474	"_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4");
Linus Nielsen Feltzing	951fe18	2002-05-29 09:11:04 +0000	[diff] [blame]	475
				476	void system_init(void)
				477	{
				478	/* Disable all interrupts */
				479	IPRA = 0;
				480	IPRB = 0;
				481	IPRC = 0;
				482	IPRD = 0;
				483	IPRE = 0;
				484
				485	/* NMI level low, falling edge on all interrupts */
				486	ICR = 0;
Linus Nielsen Feltzing	8ca44dc	2002-09-05 07:22:37 +0000	[diff] [blame]	487
Jörg Hohensohn	4cee740	2004-03-13 11:44:48 +0000	[diff] [blame]	488	/* Enable burst and RAS down mode on DRAM */
				489	DCR \|= 0x5000;
Linus Nielsen Feltzing	a2c0afb	2002-09-05 10:21:48 +0000	[diff] [blame]	490
				491	/* Activate Warp mode (simultaneous internal and external mem access) */
				492	BCR \|= 0x2000;
Linus Nielsen Feltzing	266f411	2003-10-27 10:30:12 +0000	[diff] [blame]	493
				494	/* Bus state controller initializations. These are only necessary when
				495	running from flash. The correct settings for player models are not
				496	verified, so we only do this for the recorder. */
				497	#ifdef HAVE_RECORDING
				498	WCR1 = 0x4000; /* Long wait states for CS6 (ATA), short for the rest. */
				499	WCR3 = 0x8000; /* WAIT is pulled up, 1 state inserted for CS6 */
				500	#endif
Linus Nielsen Feltzing	951fe18	2002-05-29 09:11:04 +0000	[diff] [blame]	501	}