Blame - gdb/sh.h - rockbox

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Björn Stenberg	d42d78f	2002-04-15 08:35:08 +0000	[diff] [blame]	1	/***************************************************************************
				2	* __________ __ ___.
				3	* Open \______ \ ____ ____ \| \| _\_ \|__ _______ ___
				4	* Source \| _// _ \_/ ___\\| \|/ /\| __ \ / _ \ \/ /
				5	* Jukebox \| \| ( <_> ) \___\| < \| \_\ ( <_> > < <
				6	* Firmware \|____\|_ /\____/ \___ >__\|_ \\|___ /\____/__/\_ \
				7	* \/ \/ \/ \/ \/
				8	* $Id$
				9	*
				10	* Copyright (C) 2002 by Linus Nielsen Feltzing
				11	*
				12	* All files in this archive are subject to the GNU General Public License.
				13	* See the file COPYING in the source tree root for full license agreement.
				14	*
				15	* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
				16	* KIND, either express or implied.
				17	*
				18	****************************************************************************/
				19	#ifndef SH_H_INCLUDED
				20	#define SH_H_INCLUDED
				21
				22	/* Support for Serial I/O using on chip uart */
				23
				24	#define SMR0 ((volatile unsigned char )(0x05FFFEC0)) /* Ch 0 serial mode */
				25	#define BRR0 ((volatile unsigned char )(0x05FFFEC1)) /* Ch 0 bit rate */
				26	#define SCR0 ((volatile unsigned char )(0x05FFFEC2)) /* Ch 0 serial ctrl */
				27	#define TDR0 ((volatile unsigned char )(0x05FFFEC3)) /* Ch 0 transmit data */
				28	#define SSR0 ((volatile unsigned char )(0x05FFFEC4)) /* Ch 0 serial status */
				29	#define RDR0 ((volatile unsigned char )(0x05FFFEC5)) /* Ch 0 receive data */
				30
				31	#define SMR1 ((volatile unsigned char )(0x05FFFEC8)) /* Ch 1 serial mode */
				32	#define BRR1 ((volatile unsigned char )(0x05FFFEC9)) /* Ch 1 bit rate */
				33	#define SCR1 ((volatile unsigned char )(0x05FFFECA)) /* Ch 1 serial ctrl */
				34	#define TDR1 ((volatile unsigned char )(0x05FFFECB)) /* Ch 1 transmit data */
				35	#define SSR1 ((volatile unsigned char )(0x05FFFECC)) /* Ch 1 serial status */
				36	#define RDR1 ((volatile unsigned char )(0x05FFFECD)) /* Ch 1 receive data */
				37
				38	/*
				39	* Serial mode register bits
				40	*/
				41
				42	#define SYNC_MODE 0x80
				43	#define SEVEN_BIT_DATA 0x40
				44	#define PARITY_ON 0x20
				45	#define ODD_PARITY 0x10
				46	#define STOP_BITS_2 0x08
				47	#define ENABLE_MULTIP 0x04
				48	#define PHI_64 0x03
				49	#define PHI_16 0x02
				50	#define PHI_4 0x01
				51
				52	/*
				53	* Serial control register bits
				54	*/
				55	#define SCI_TIE 0x80 /* Transmit interrupt enable */
				56	#define SCI_RIE 0x40 /* Receive interrupt enable */
				57	#define SCI_TE 0x20 /* Transmit enable */
				58	#define SCI_RE 0x10 /* Receive enable */
				59	#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
				60	#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
				61	#define SCI_CKE1 0x02 /* Clock enable 1 */
				62	#define SCI_CKE0 0x01 /* Clock enable 0 */
				63
				64	/*
				65	* Serial status register bits
				66	*/
				67	#define SCI_TDRE 0x80 /* Transmit data register empty */
				68	#define SCI_RDRF 0x40 /* Receive data register full */
				69	#define SCI_ORER 0x20 /* Overrun error */
				70	#define SCI_FER 0x10 /* Framing error */
				71	#define SCI_PER 0x08 /* Parity error */
				72	#define SCI_TEND 0x04 /* Transmit end */
				73	#define SCI_MPB 0x02 /* Multiprocessor bit */
				74	#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
				75
				76	/*
				77	* Port Registers
				78	*/
				79	#define PADR ((volatile unsigned short )(0x5ffffc0)) /* Port A Data */
				80	#define PAIOR ((volatile unsigned short )(0x5ffffc4)) /* Port A I/O */
				81	#define PACR1 ((volatile unsigned short )(0x5ffffc8)) /* Port A ctrl 1 */
				82	#define PACR2 ((volatile unsigned short )(0x5ffffca)) /* Port A ctrl 2 */
				83
				84	#define PBDR ((volatile unsigned short )(0x5ffffc2)) /* Port B Data */
				85	#define PBIOR ((volatile unsigned short )(0x5ffffc6)) /* Port B I/O */
				86	#define PBCR1 ((volatile unsigned short )(0x5ffffcc)) /* Port B ctrl 1 */
				87	#define PBCR2 ((volatile unsigned short )(0x5ffffce)) /* Port B ctrl 2 */
				88
				89	#define CASCR ((volatile unsigned short )(0x5ffffee)) /* CAS strobe pin */
				90
				91	#define PB15MD PB15MD1\|PB14MD0
				92	#define PB14MD PB14MD1\|PB14MD0
				93	#define PB13MD PB13MD1\|PB13MD0
				94	#define PB12MD PB12MD1\|PB12MD0
				95	#define PB11MD PB11MD1\|PB11MD0
				96	#define PB10MD PB10MD1\|PB10MD0
				97	#define PB9MD PB9MD1\|PB9MD0
				98	#define PB8MD PB8MD1\|PB8MD0
				99
				100	#define PB_TXD1 PB11MD1
				101	#define PB_RXD1 PB10MD1
				102	#define PB_TXD0 PB9MD1
				103	#define PB_RXD0 PB8MD1
				104
				105	#define PB7MD PB7MD1\|PB7MD0
				106	#define PB6MD PB6MD1\|PB6MD0
				107	#define PB5MD PB5MD1\|PB5MD0
				108	#define PB4MD PB4MD1\|PB4MD0
				109	#define PB3MD PB3MD1\|PB3MD0
				110	#define PB2MD PB2MD1\|PB2MD0
				111	#define PB1MD PB1MD1\|PB1MD0
				112	#define PB0MD PB0MD1\|PB0MD0
				113
				114	/* Bus state controller registers */
				115	#define BCR ((volatile unsigned short )(0x5ffffa0)) /* Bus control */
				116	#define WCR1 ((volatile unsigned short )(0x5ffffa2)) /* Wait state ctrl 1 */
				117	#define WCR2 ((volatile unsigned short )(0x5ffffa4)) /* Wait state ctrl 2 */
				118	#define WCR3 ((volatile unsigned short )(0x5ffffa6)) /* Wait state ctrl 3 */
				119	#define DCR ((volatile unsigned short )(0x5ffffa8)) /* DRAM area ctrl */
				120	#define PCR ((volatile unsigned short )(0x5ffffaa)) /* Parity control */
				121	#define RCR ((volatile unsigned short )(0x5ffffae)) /* Refresh control */
				122	#define RTCSR ((volatile unsigned short )(0x5ffffae)) /* Refresh timer
				123	control/status */
				124	#define RTCNT ((volatile unsigned short )(0x5ffffb0)) /* Refresh timer cnt */
				125	#define RTCOR ((volatile unsigned short )(0x5ffffb2)) /* Refresh time
				126	constant */
				127
				128	/* Interrupt controller registers */
				129	#define IPRA ((volatile unsigned short )(0x5ffff84)) /* Priority A */
				130	#define IPRB ((volatile unsigned short )(0x5ffff86)) /* Priority B */
				131	#define IPRC ((volatile unsigned short )(0x5ffff88)) /* Priority C */
				132	#define IPRD ((volatile unsigned short )(0x5ffff88)) /* Priority D */
				133	#define IPRE ((volatile unsigned short )(0x5ffff8c)) /* Priority E */
				134	#define ICR ((volatile unsigned short )(0x5ffff8e)) /* Interrupt Control */
				135
				136	/* ITU registers */
				137	#define TSTR ((volatile unsigned char )(0x5ffff00)) /* Timer Start */
				138	#define TSNC ((volatile unsigned char )(0x5ffff01)) /* Timer Synchro */
				139	#define TMDR ((volatile unsigned char )(0x5ffff02)) /* Timer Mode */
				140	#define TFCR ((volatile unsigned char )(0x5ffff03)) /* Timer Function Ctrl */
				141	#define TOCR ((volatile unsigned char )(0x5ffff31)) /* Timer Output Ctrl */
				142
				143	#define TCR0 ((volatile unsigned char )(0x5ffff04)) /* Timer 0 Ctrl */
				144	#define TIOR0 ((volatile unsigned char )(0x5ffff05)) /* Timer 0 I/O Ctrl */
				145	#define TIER0 ((volatile unsigned char )(0x5ffff06)) /* Timer 0 Int Enable */
				146	#define TSR0 ((volatile unsigned char )(0x5ffff07)) /* Timer 0 Status */
				147	#define TCNT0 ((volatile unsigned short )(0x5ffff08)) /* Timer 0 Count */
				148	#define GRA0 ((volatile unsigned short )(0x5ffff0a)) /* Timer 0 GRA */
				149	#define GRB0 ((volatile unsigned short )(0x5ffff0c)) /* Timer 0 GRB */
				150
				151	#define TCR1 ((volatile unsigned char )(0x5ffff0e)) /* Timer 1 Ctrl */
				152	#define TIOR1 ((volatile unsigned char )(0x5ffff0f)) /* Timer 1 I/O Ctrl */
				153	#define TIER1 ((volatile unsigned char )(0x5ffff10)) /* Timer 1 Int Enable */
				154	#define TSR1 ((volatile unsigned char )(0x5ffff11)) /* Timer 1 Status */
				155	#define TCNT1 ((volatile unsigned short )(0x5ffff12)) /* Timer 1 Count */
				156	#define GRA1 ((volatile unsigned short )(0x5ffff14)) /* Timer 1 GRA */
				157	#define GRB1 ((volatile unsigned short )(0x5ffff16)) /* Timer 1 GRB */
				158
				159	#define TCR2 ((volatile unsigned char )(0x5ffff18)) /* Timer 2 Ctrl */
				160	#define TIOR2 ((volatile unsigned char )(0x5ffff19)) /* Timer 2 I/O Ctrl */
				161	#define TIER2 ((volatile unsigned char )(0x5ffff1a)) /* Timer 2 Int Enable */
				162	#define TSR2 ((volatile unsigned char )(0x5ffff1b)) /* Timer 2 Status */
				163	#define TCNT2 ((volatile unsigned short )(0x5ffff1c)) /* Timer 2 Count */
				164	#define GRA2 ((volatile unsigned short )(0x5ffff1e)) /* Timer 2 GRA */
				165	#define GRB2 ((volatile unsigned short )(0x5ffff20)) /* Timer 2 GRB */
				166
				167	#define TCR3 ((volatile unsigned char )(0x5ffff22)) /* Timer 3 Ctrl */
				168	#define TIOR3 ((volatile unsigned char )(0x5ffff23)) /* Timer 3 I/O Ctrl */
				169	#define TIER3 ((volatile unsigned char )(0x5ffff24)) /* Timer 3 Int Enable */
				170	#define TSR3 ((volatile unsigned char )(0x5ffff25)) /* Timer 3 Status */
				171	#define TCNT3 ((volatile unsigned short )(0x5ffff26)) /* Timer 3 Count */
				172	#define GRA3 ((volatile unsigned short )(0x5ffff28)) /* Timer 3 GRA */
				173	#define GRB3 ((volatile unsigned short )(0x5ffff2a)) /* Timer 3 GRB */
				174	#define BRA3 ((volatile unsigned short )(0x5ffff2c)) /* Timer 3 BRA */
				175	#define BRB3 ((volatile unsigned short )(0x5ffff2e)) /* Timer 3 BRB */
				176
				177	#define TCR4 ((volatile unsigned char )(0x5ffff32)) /* Timer 4 Ctrl */
				178	#define TIOR4 ((volatile unsigned char )(0x5ffff33)) /* Timer 4 I/O Ctrl */
				179	#define TIER4 ((volatile unsigned char )(0x5ffff34)) /* Timer 4 Int Enable */
				180	#define TSR4 ((volatile unsigned char )(0x5ffff35)) /* Timer 4 Status */
				181	#define TCNT4 ((volatile unsigned short )(0x5ffff36)) /* Timer 4 Count */
				182	#define GRA4 ((volatile unsigned short )(0x5ffff38)) /* Timer 4 GRA */
				183	#define GRB4 ((volatile unsigned short )(0x5ffff3a)) /* Timer 4 GRB */
				184	#define BRA4 ((volatile unsigned short )(0x5ffff3c)) /* Timer 4 BRA */
				185	#define BRB4 ((volatile unsigned short )(0x5ffff3e)) /* Timer 4 BRB */
				186
				187	#endif