Gitiles
Code Review Sign In
gerrit.rockbox.org / rockbox / 3d3f419b1a2ba70d2283531a1f695eec95833a27 / . / utils / disassembler / arm / disasm_arm.c
blob: 14e72d958393f0792b6217ecc5014cc62ea51ce9 [file] [log] [blame]
Rafaël Carréc0bd4172010-06-17 16:59:51 +0000[diff] [blame]1#include <stdio.h>
2#include <string.h>
3#include <stdint.h>
4
5#define ULONG uint32_t
6#define UCHAR uint8_t
7
8#define FRMT "0x%x" // "0x%x"
9#define SHFTFRMC "%s %s #%d" // "%s %s %d"
10#define SHFTFRMR "%s %s %s" // "%s %s %s"
11//#define FRMT "0x%x"
12//#define SHFTFRMC "%s %s %d"
13//#define SHFTFRMR "%s %s %s"
14
15char *cond[16] = { "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "", "nv" };
16char *cnd1[16] = { "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", " ", "nv" };
17char *opcd[16] = {"and","eor","sub","rsb","add","adc","sbc","rsc","tst","teq","cmp","cmn","orr","mov","bic","mvn" };
18char setc[32] = {0,115,0,115,0,115,0,115,0,115,0,115,0,115,0,115,0, 0 ,0, 0 ,0, 0 ,0, 0 ,0,115,0,115,0,115,0,115 };
19char *regs[16] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" };
20
21char *shfts[4] = { "lsl", "lsr", "asr", "ror" };
22
23/*
2431-28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
25Cond 0 0 I ---Opcode--- S |----Rn----- ----Rd----- --------Operand 2-------- Data Processing /PSR Transfer
26Cond 0 0 0 0 | 0 0 A S |----Rd----- ----Rn----- ---Rs---- 1 0 0 1 --Rm--- Multiply
27Cond 0 0 0 0 | 1 U A S |---RdHi---- ---RdLo---- ---Rn---- 1 0 0 1 --Rm--- Multiply Long
28Cond 0 0 0 1 | 0 B 0 0 |----Rn----- ----Rd----- 0 0 0 0 1 0 0 1 --Rm--- Single Data Swap
29Cond 0 0 0 1 | 0 0 1 0 |1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 --Rn--- Branch and Exchange
30Cond 0 0 0 P | U 0 W L |----Rn----- ----Rd----- 0 0 0 0 1 S H 1 --Rm--- Halfword Data Transfer: register offset
31Cond 0 0 0 P | U 1 W L |----Rn----- ----Rd----- --Offset- 1 S H 1 -Offset Halfword Data Transfer: immediate offset
32Cond 0 1 I P | U B W L |----Rn----- ----Rd----- --------Offset----------- Single Data Transfer
33Cond 0 1 1 1 | x x x x |x x x x x x x x x x x x x x x 1 x x x x Undefined
34Cond 1 0 0 P | U S W L |----Rn----- -----------Register List------------- Block Data Transfer
35Cond 1 0 1 L | -------------------------Offset------------------------------ Branch
36Cond 1 1 0 P | U N W L |----Rn----- ----CRd---- ---CP#--- -----Offset---- Coprocessor Data Transfer
37Cond 1 1 1 0 | --CP Opc---|----CRn---- ----CRd---- ---CP#--- -CP-- 0 --CRm-- Coprocessor Data Operation
38Cond 1 1 1 0 | CP Opc L |----CRn---- ----Rd----- ---CP#--- -CP-- 1 --CRm-- Coprocessor Register Transfer
39Cond 1 1 1 1 | x x x x |x x x x x x x x x x x x x x x x x x x x Software Interrupt
40
410x04200000
420001 0 0 0 0 0 1 1 0 6 e 1 1 1 0 1 8
43================================================================================
44Cond 0 1 I P | U B W L |----Rn----- ----Rd----- --------Offset----------- Single Data Transfer
45
46
47EQ 0 Z set equal
48NE 1 Z clear not equal
49CS 2 C set unsigned higher or same
50CC 3 C clear unsigned lower
51MI 4 N set negative
52PL 5 N clear positive or zero
53VS 6 V set overflow
54VC 7 V clear no overflow
55HI 8 C set and Z clear unsigned higher
56LS 9 C clear or Z set unsigned lower or same
57GE A N equals V greater or equal
58LT B N not equal to V less than
59GT C Z clear AND (N equals V) greater than
60LE D Z set OR (N not equal to V) less than or equal
61AL E (ignored) always
62
63AND 0 operand1 AND operand2
64EOR 1 operand1 EOR operand2
65SUB 2 operand1 - operand2
66RSB 3 operand2 - operand1
67ADD 4 operand1 + operand2
68ADC 5 operand1 + operand2 + carry
69SBC 6 operand1 - operand2 + carry - 1
70RSC 7 operand2 - operand1 + carry - 1
71TST 8 AND, but result is not written
72TEQ 9 as EOR, but result is not written
73CMP A as SUB, but result is not written
74CMN B as ADD, but result is not written
75ORR C operand1 OR operand2
76MOV D operand2 (operand1 is ignored)
77BIC E operand1 AND NOT operand2 (Bit clear)
78MVN F NOT operand2 (operand1 is ignored)
79*/
80
81void multiply_stg(char *stg, ULONG val)
82{
83 if((val&0xc00000) == 0) // simple mul
84 {
85 if(val & 0x100000) // set condition flags
86 if(val & 0x200000) sprintf(stg+strlen(stg), "mla%ss ", cond[val>>28]);
87 else sprintf(stg+strlen(stg), "mul%ss ", cond[val>>28]);
88 else
89 if(val & 0x200000) sprintf(stg+strlen(stg), "mla%s ", cnd1[val>>28]);
90 else sprintf(stg+strlen(stg), "mul%s ", cnd1[val>>28]);
91
92 if(val & 0x200000) // accumulate
93 sprintf(stg+strlen(stg), "%s, %s, %s, %s", regs[(val>>16)&15], regs[(val>>0)&15], regs[(val>>8)&15], regs[(val>>12)&15]);
94 else
95 sprintf(stg+strlen(stg), "%s, %s, %s", regs[(val>>16)&15], regs[(val>>0)&15], regs[(val>>8)&15]);
96 }
97 else
98 {
99 if(val & 0x100000) // set condition flags
100 if(val & 0x200000) // accumulate
101 if(val & 0x400000) sprintf(stg+strlen(stg), "smlal%ss ", cond[val>>28]);
102 else sprintf(stg+strlen(stg), "umlal%ss ", cond[val>>28]);
103 else
104 if(val & 0x400000) sprintf(stg+strlen(stg), "smull%ss ", cond[val>>28]);
105 else sprintf(stg+strlen(stg), "umull%ss ", cond[val>>28]);
106 else
107 if(val & 0x200000)
108 if(val & 0x400000) sprintf(stg+strlen(stg), "smlal%s ", cond[val>>28]);
109 else sprintf(stg+strlen(stg), "umlal%s ", cond[val>>28]);
110 else
111 if(val & 0x400000) sprintf(stg+strlen(stg), "smull%s ", cond[val>>28]);
112 else sprintf(stg+strlen(stg), "umull%s ", cond[val>>28]);
113
114 sprintf(stg+strlen(stg), "%s, %s, %s, %s", regs[(val>>12)&15], regs[(val>>16)&15], regs[(val>>0)&15], regs[(val>>8)&15]);
115 }
116}
117
118void halfword_stg(char *stg, ULONG val)
119{
120 ULONG off = ((val>>4) & 0xf0) + (val & 0x0f);
121
122 if(val & 0x100000) sprintf(stg+strlen(stg), "ldr%s", cond[val>>28]);
123 else sprintf(stg+strlen(stg), "str%s", cond[val>>28]);
124
125 switch((val>>5) & 3) // SWP, HW, SB, SH
126 {
127 case 0: sprintf(stg+strlen(stg), "error: SWP"); break;
128 case 1: sprintf(stg+strlen(stg), "h "); break;
129 case 2: sprintf(stg+strlen(stg), "sb "); break;
130 case 3: sprintf(stg+strlen(stg), "sh "); break;
131 }
132
133 if(val & 0x400000) // immidiate offset
134 if(val & 0x1000000) // pre index
135 if(val & 0x200000) // write back
136 if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s, "FRMT"]!", regs[(val>>12)&15], regs[(val>>16)&15], off);
137 else sprintf(stg+strlen(stg), "%s, [%s, -"FRMT"]!", regs[(val>>12)&15], regs[(val>>16)&15], off);
138 else
139 if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s, "FRMT"]", regs[(val>>12)&15], regs[(val>>16)&15], off);
140 else sprintf(stg+strlen(stg), "%s, [%s, -"FRMT"]", regs[(val>>12)&15], regs[(val>>16)&15], off);
141 else
142 if(val & 0x200000) // write back
143 sprintf(stg+strlen(stg), "error 'write back' on post indexed");
144 else
145 if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s], "FRMT, regs[(val>>12)&15], regs[(val>>16)&15], off);
146 else sprintf(stg+strlen(stg), "%s, [%s], -"FRMT, regs[(val>>12)&15], regs[(val>>16)&15], off);
147 else
148 if(val & 0x1000000) // pre index
149 if(val & 0x200000) // write back
150 if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s, %s]!", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
151 else sprintf(stg+strlen(stg), "%s, [%s, -%s]!", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
152 else
153 if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s, %s]", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
154 else sprintf(stg+strlen(stg), "%s, [%s, -%s]", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
155 else
156 if(val & 0x200000) // write back
157 sprintf(stg+strlen(stg), "error 'write back' on post indexed");
158 else
159 if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s], %s", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
160 else sprintf(stg+strlen(stg), "%s, [%s], -%s", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
161}
162
163void branch_stg(char *stg, ULONG val, ULONG pos)
164{
165 ULONG off = pos + (((int32_t)val << 8) >> 6) + 8;
166
167 if((val & 0x0ffffff0) == 0x012fff10) // bx instruction
168 { sprintf(stg+strlen(stg), "bx%s %s", cond[val>>28], regs[val&15]); }
169 else
170 {
171 if(((val>>24)&15) == 10) sprintf(stg+strlen(stg), "b%s ", cond[val>>28]);
172 else sprintf(stg+strlen(stg), "bl%s ", cond[val>>28]);
173
174 sprintf(stg+strlen(stg), "0x%x", off);
175 }
176}
177
178void opcode_stg(char *stg, ULONG val, ULONG off)
179{
180 ULONG des, op1;
181 char op2[80];
182 char *st = stg + strlen(stg);
183
184 if(((val & 0x0ffffff0) == 0x012fff10) && (val & 16))
185 { branch_stg(stg, val, off); return; }
186 else if(((val & 0x0f000000) == 0x00000000) && ((val & 0xf0) == 0x90))
187 { multiply_stg(stg, val); return; }
188 else if(((val & 0x0f000000) <= 0x01000000) && ((val & 0x90) == 0x90) && ((val & 0xf0) > 0x90) && ((val & 0x01200000) != 0x00200000))
189 { halfword_stg(stg, val); return; }
190
191 sprintf(stg+strlen(stg), "%s%s%s ", opcd[(val>>21) & 15], cond[val>>28], setc[(val>>20) & 31]?"s":" ");
192
193 des = (val>>12) & 15;
194 op1 = (val>>16) & 15;
195
196 if(val & 0x2000000) // immidiate
197 {
198 off = (ULONG)((uint64_t)(val&0xff) << (32 - 2 * ((val >> 8) & 15))) | ((val&0xff) >> 2 * ((val >> 8) & 15));
199 sprintf(op2, FRMT" ", off);
200 }
201 else
202 {
203 if(val & 16) // shift type
204 sprintf(op2, SHFTFRMR, regs[val&15], shfts[(val>>5)&3], regs[(val>>8)&15]);
205 else
206 if((val>>7) & 31)
207 sprintf(op2, SHFTFRMC, regs[val&15], shfts[(val>>5)&3], (val>>7) & 31);
208 else
209 sprintf(op2, "%s ", regs[val&15]);
210 }
211
212 switch((val>>21) & 15)
213 {
214 case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 12:
215 case 14: sprintf(stg+strlen(stg), "%s, %s, %s", regs[des], regs[op1], op2); break;
216
217 case 8: case 9: case 10:
218 case 11: if(val & 0x100000) // set status
219 sprintf(stg+strlen(stg), "%s, %s", regs[op1], op2); // standard TEQ,TST,CMP,CMN
220 else
221 { //special MRS/MSR opcodes
222 if((((val>>23) & 31) == 2) && ((val & 0x3f0fff) == 0x0f0000))
223 { sprintf(st, "mrs%s %s, %s", cnd1[val>>28], regs[des], val&0x400000?"SPSR_xx":"CPSR"); }
224 else
225 if((((val>>23) & 31) == 2) && ((val & 0x30fff0) == 0x20f000))
226 { sprintf(st, "msr%s %s, %s", cnd1[val>>28], val&0x400000?"SPSR_xx":"CPSR", regs[val&15]); }
227 else
228 if((((val>>23) & 31) == 6) && ((val & 0x30f000) == 0x20f000))
229 { sprintf(st, "msr%s %s, %s", cnd1[val>>28], val&0x400000?"SPSR_xx":"CPSR_cf", op2); }
230 else
231 if((((val>>23) & 31) == 2) && ((val & 0x300ff0) == 0x000090))
232 { sprintf(st, "swp%s%s %s, %s, [%s]", val&0x400000?"b":"", cnd1[val>>28], regs[(val>>12)&15], regs[val&15], regs[(val>>16)&15]); }
233 else
234 { sprintf(stg+strlen(stg), "??????????????"); }
235 } break;
236 case 13:
237 case 15: sprintf(stg+strlen(stg), "%s, %s", regs[des], op2); break;
238 }
239}
240
241void opcode_cop(char *stg, ULONG val, ULONG off)
242{
243 char* op;
244 int opcode1 = (val >> 21) & 0x7;
245 int CRn = (val >> 16) & 0xf;
246 int Rd = (val >> 12) & 0xf;
247 int cp_num = (val >> 8) & 0xf;
248 int opcode2 = (val >> 5) & 0x7;
249 int CRm = val & 0xf;
250
251
252// ee073f5e mcr 15, 0, r3, cr7, cr14, {2}
253
254 if (val & (1<<4)) {
255 if (val & (1<<20)) {
256 op = "mrc";
257 } else {
258 op = "mcr";
259 }
260 opcode1 = (val >> 21) & 0x7;
261 CRn = (val >> 16) & 0xf;
262 Rd = (val >> 12) & 0xf;
263 cp_num = (val >> 8) & 0xf;
264 opcode2 = (val >> 5) & 0x7;
265 CRm = val & 0xf;
266
267 sprintf(stg+strlen(stg), "%s%s %d, %d, r%d, cr%d, cr%d, {%d}", op, cnd1[val>>28], cp_num, opcode1, Rd, CRn, CRm, opcode2);
268 } else {
269 op = "cdp";
270
271 opcode1 = (val >> 20) & 0xf;
272 CRn = (val >> 16) & 0xf;
273 Rd = (val >> 12) & 0xf;
274 cp_num = (val >> 8) & 0xf;
275 opcode2 = (val >> 5) & 0x7;
276 CRm = val & 0xf;
277
278 sprintf(stg+strlen(stg), "%s%s %d, %d, cr%d, cr%d, cr%d, {%d}", op, cnd1[val>>28], cp_num, opcode1, Rd, CRn, CRm, opcode2);
279 }
280
281}
282
283
284void single_data(char *stg, ULONG val)
285{
286 char op2[80];
287
288 if(((val & 0x0e000000) == 0x06000000) && (val & 16))
289 { sprintf(stg+strlen(stg), "undef%s", cond[val>>28]);
290 return;
291 }
292
293 if(val & 0x400000)
294 if(val & 0x100000) sprintf(stg+strlen(stg), "ldr%sb ", cond[val>>28]);
295 else sprintf(stg+strlen(stg), "str%sb ", cond[val>>28]);
296 else
297 if(val & 0x100000) sprintf(stg+strlen(stg), "ldr%s ", cnd1[val>>28]);
298 else sprintf(stg+strlen(stg), "str%s ", cnd1[val>>28]);
299
300 if(val & 0x2000000) {// reg offset
301 if(val & 16) // shift type
302 sprintf(op2, "error: reg defined shift");
303 else
304 if((val>>7) & 31)
305 sprintf(op2, SHFTFRMC, regs[val&15], shfts[(val>>5)&3], (val>>7) & 31);
306 else
307 sprintf(op2, "%s", regs[val&15]);
308 }
309
310 if(val & 0x2000000) // reg offset
311 if(val & 0x1000000) // pre index
312 if(val & 0x800000) // up offset (+)
313 if(val & 0x200000) // write back
314 sprintf(stg+strlen(stg), "%s, [%s, %s]!", regs[(val>>12)&15], regs[(val>>16)&15], op2);
315 else
316 sprintf(stg+strlen(stg), "%s, [%s, %s]", regs[(val>>12)&15], regs[(val>>16)&15], op2);
317 else
318 if(val & 0x200000) // write back
319 sprintf(stg+strlen(stg), "%s, [%s, -%s]!", regs[(val>>12)&15], regs[(val>>16)&15], op2);
320 else
321 sprintf(stg+strlen(stg), "%s, [%s, -%s]", regs[(val>>12)&15], regs[(val>>16)&15], op2);
322 else
323 if(val & 0x200000) // write back
324 sprintf(stg+strlen(stg), "error 'write back' set");
325 else
326 if(val & 0x800000) // up offset (+)
327 sprintf(stg+strlen(stg), "%s, [%s], %s", regs[(val>>12)&15], regs[(val>>16)&15], op2);
328 else
329 sprintf(stg+strlen(stg), "%s, [%s], -%s", regs[(val>>12)&15], regs[(val>>16)&15], op2);
330 else
331 if(val & 0x1000000) // pre index
332 if(val & 0x800000) // up offset (+)
333 if(val & 0x200000) // write back
334 if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s, "FRMT"]!", regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
335 else sprintf(stg+strlen(stg), "%s, [%s]!", regs[(val>>12)&15], regs[(val>>16)&15]);
336 else
337 if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s, "FRMT"]", regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
338 else sprintf(stg+strlen(stg), "%s, [%s]", regs[(val>>12)&15], regs[(val>>16)&15]);
339 else
340 if(val & 0x200000) // write back
341 if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s, -"FRMT"]!", regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
342 else sprintf(stg+strlen(stg), "%s, [%s]!", regs[(val>>12)&15], regs[(val>>16)&15]);
343 else
344 if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s, -"FRMT"]", regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
345 else sprintf(stg+strlen(stg), "%s, [%s]", regs[(val>>12)&15], regs[(val>>16)&15]);
346 else
347 if(val & 0x200000) // write back
348 sprintf(stg+strlen(stg), "error 'write back' set");
349 else
350 if(val & 0x800000) // up offset (+)
351 if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s], "FRMT, regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
352 else sprintf(stg+strlen(stg), "%s, [%s]", regs[(val>>12)&15], regs[(val>>16)&15]);
353 else
354 if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s], -"FRMT, regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
355 else sprintf(stg+strlen(stg), "%s, [%s]", regs[(val>>12)&15], regs[(val>>16)&15]);
356}
357
358void block_data(char *stg, ULONG val)
359{
360 char lst[80];
361 int i;
362
363 strcpy(lst, "{");
364 for(i=0; i<16; i++)
365 if(val & (1<<i))
366 sprintf(lst+strlen(lst), "%s, ", regs[i]);
367 if(strlen(lst)>2)
368 strcpy(lst+strlen(lst)-2, "}");
369 else
370 strcpy(lst+strlen(lst), "}");
371
372 if(val & 0x400000) // load psr or force user mode
373 strcpy(lst+strlen(lst), "^");
374
375
376 if(val & 0x100000) // load
377 if(val & 0x1000000) // pre offset
378 if(val & 0x800000) sprintf(stg+strlen(stg), "ldm%sib ", cond[val>>28]);
379 else sprintf(stg+strlen(stg), "ldm%sdb ", cond[val>>28]);
380 else
381 if(val & 0x800000) sprintf(stg+strlen(stg), "ldm%sia ", cond[val>>28]);
382 else sprintf(stg+strlen(stg), "ldm%sda ", cond[val>>28]);
383 else
384 if(val & 0x1000000)
385 if(val & 0x800000) sprintf(stg+strlen(stg), "stm%sib ", cond[val>>28]);
386 else sprintf(stg+strlen(stg), "stm%sdb ", cond[val>>28]);
387 else
388 if(val & 0x800000) sprintf(stg+strlen(stg), "stm%sia ", cond[val>>28]);
389 else sprintf(stg+strlen(stg), "stm%sda ", cond[val>>28]);
390
391 switch((val>>21)&3)
392 {
393 case 0: sprintf(stg+strlen(stg), "%s, %s", regs[(val>>16)&15], lst); break;
394 case 1: sprintf(stg+strlen(stg), "%s!, %s", regs[(val>>16)&15], lst); break;
395 case 2: sprintf(stg+strlen(stg), "%s, %s", regs[(val>>16)&15], lst); break;
396 case 3: sprintf(stg+strlen(stg), "%s!, %s", regs[(val>>16)&15], lst); break;
397 }
398}
399
400void dis_asm(ULONG off, ULONG val, char *stg)
401{
402 sprintf(stg, "%6x: %08x ", off, val);
403
404 switch((val >> 24) & 15)
405 {
406 case 0:
407 case 1:
408 case 2:
409 case 3: opcode_stg(stg, val, off); break;
410 case 4:
411 case 5:
412 case 6:
413 case 7: single_data(stg, val); break;
414 case 8:
415 case 9: block_data(stg, val); break;
416 case 10:
417 case 11: branch_stg(stg, val, off); break;
418 case 12:
419 case 13: sprintf(stg+strlen(stg), "cop%s", cnd1[val>>28]); break;
420 case 14: opcode_cop(stg, val, off); break;
421 case 15: sprintf(stg+strlen(stg), "swi%s", cnd1[val>>28]); break;
422 }
423}