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Amaury Pouly08fb3f62011-05-01 13:02:46 +00001/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright © 2011 by Amaury Pouly
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#ifndef CLKCTRL_IMX233_H
22#define CLKCTRL_IMX233_H
23
24#include "config.h"
25#include "system.h"
26#include "cpu.h"
27
28#define HW_CLKCTRL_BASE 0x80040000
29
Amaury Pouly617d1e92011-06-30 17:31:40 +000030#define HW_CLKCTRL_PLLCTRL0 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x0))
Amaury Poulydd865bc2011-12-03 15:34:40 +000031#define HW_CLKCTRL_PLLCTRL0__POWER (1 << 16)
Amaury Poulyb25d6e02011-09-14 11:50:06 +000032#define HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS (1 << 18)
33#define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BP 20
34#define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BM (3 << 20)
Amaury Pouly617d1e92011-06-30 17:31:40 +000035
36#define HW_CLKCTRL_PLLCTRL1 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x10))
37
38#define HW_CLKCTRL_CPU (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x20))
39#define HW_CLKCTRL_CPU__DIV_CPU_BP 0
40#define HW_CLKCTRL_CPU__DIV_CPU_BM 0x3f
Amaury Poulydd865bc2011-12-03 15:34:40 +000041#define HW_CLKCTRL_CPU__INTERRUPT_WAIT (1 << 12)
42#define HW_CLKCTRL_CPU__DIV_XTAL_BP 16
43#define HW_CLKCTRL_CPU__DIV_XTAL_BM (0x3ff << 16)
44#define HW_CLKCTRL_CPU__DIV_XTAL_FRAC_EN (1 << 26)
Amaury Pouly617d1e92011-06-30 17:31:40 +000045#define HW_CLKCTRL_CPU__BUSY_REF_CPU (1 << 28)
46
47#define HW_CLKCTRL_HBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x30))
Amaury Poulydd865bc2011-12-03 15:34:40 +000048#define HW_CLKCTRL_HBUS__DIV_BP 0
49#define HW_CLKCTRL_HBUS__DIV_BM 0x1f
50#define HW_CLKCTRL_HBUS__DIV_FRAC_EN (1 << 5)
51#define HW_CLKCTRL_HBUS__SLOW_DIV_BP 16
52#define HW_CLKCTRL_HBUS__SLOW_DIV_BM (0x7 << 16)
53#define HW_CLKCTRL_HBUS__AUTO_SLOW_MODE (1 << 20)
Amaury Pouly617d1e92011-06-30 17:31:40 +000054
Amaury Poulye36b20c2011-07-03 15:18:41 +000055#define HW_CLKCTRL_XBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40))
56#define HW_CLKCTRL_XBUS__DIV_BP 0
57#define HW_CLKCTRL_XBUS__DIV_BM 0x3ff
58#define HW_CLKCTRL_XBUS__BUSY (1 << 31)
59
Amaury Pouly08fb3f62011-05-01 13:02:46 +000060#define HW_CLKCTRL_XTAL (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x50))
61#define HW_CLKCTRL_XTAL__TIMROT_CLK32K_GATE (1 << 26)
Amaury Poulyd0e8c352011-10-18 22:00:50 +000062#define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE (1 << 28)
63#define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE (1 << 30)
Amaury Pouly08fb3f62011-05-01 13:02:46 +000064
65#define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60))
Amaury Poulydd865bc2011-12-03 15:34:40 +000066#define HW_CLKCTRL_PIX__DIV_BP 0
Amaury Pouly617d1e92011-06-30 17:31:40 +000067#define HW_CLKCTRL_PIX__DIV_BM 0xfff
68
Amaury Pouly2cf33132011-06-17 22:30:58 +000069#define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70))
Amaury Poulydd865bc2011-12-03 15:34:40 +000070#define HW_CLKCTRL_SSP__DIV_BP 0
Amaury Pouly617d1e92011-06-30 17:31:40 +000071#define HW_CLKCTRL_SSP__DIV_BM 0x1ff
Amaury Pouly08fb3f62011-05-01 13:02:46 +000072
Amaury Poulydd865bc2011-12-03 15:34:40 +000073#define HW_CLKCTRL_EMI (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xa0))
74#define HW_CLKCTRL_EMI__DIV_EMI_BP 0
75#define HW_CLKCTRL_EMI__DIV_EMI_BM 0x3f
76#define HW_CLKCTRL_EMI__DIV_XTAL_BP 8
77#define HW_CLKCTRL_EMI__DIV_XTAL_BM (0xf << 8)
78#define HW_CLKCTRL_EMI__BUSY_REF_EMI (1 << 28)
79#define HW_CLKCTRL_EMI__SYNC_MODE_EN (1 << 30)
80#define HW_CLKCTRL_EMI__CLKGATE (1 << 31)
81
Amaury Pouly08fb3f62011-05-01 13:02:46 +000082#define HW_CLKCTRL_CLKSEQ (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x110))
83#define HW_CLKCTRL_CLKSEQ__BYPASS_PIX (1 << 1)
Amaury Pouly2cf33132011-06-17 22:30:58 +000084#define HW_CLKCTRL_CLKSEQ__BYPASS_SSP (1 << 5)
Amaury Poulydd865bc2011-12-03 15:34:40 +000085#define HW_CLKCTRL_CLKSEQ__BYPASS_EMI (1 << 6)
Amaury Pouly617d1e92011-06-30 17:31:40 +000086#define HW_CLKCTRL_CLKSEQ__BYPASS_CPU (1 << 7)
Amaury Pouly2cf33132011-06-17 22:30:58 +000087
88#define HW_CLKCTRL_FRAC (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xf0))
89#define HW_CLKCTRL_FRAC_CPU (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf0))
90#define HW_CLKCTRL_FRAC_EMI (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf1))
91#define HW_CLKCTRL_FRAC_PIX (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf2))
92#define HW_CLKCTRL_FRAC_IO (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf3))
93#define HW_CLKCTRL_FRAC_XX__XXDIV_BM 0x3f
94#define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6)
95#define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7)
Amaury Pouly08fb3f62011-05-01 13:02:46 +000096
97#define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120))
98#define HW_CLKCTRL_RESET_CHIP 0x2
99#define HW_CLKCTRL_RESET_DIG 0x1
100
101enum imx233_clock_t
102{
Amaury Poulydd865bc2011-12-03 15:34:40 +0000103 CLK_PIX, /* freq, div, frac, bypass, enable */
104 CLK_SSP, /* freq, div, bypass, enable */
105 CLK_IO, /* freq, frac */
106 CLK_CPU, /* freq, div, frac, bypass */
107 CLK_HBUS, /* freq, div, frac */
108 CLK_PLL, /* freq */
109 CLK_XTAL, /* freq */
110 CLK_EMI, /* freq */
111 CLK_XBUS, /* freq, div */
Amaury Pouly08fb3f62011-05-01 13:02:46 +0000112};
113
Amaury Poulydd865bc2011-12-03 15:34:40 +0000114enum imx233_xtal_clk_t
Amaury Poulyd0e8c352011-10-18 22:00:50 +0000115{
116 XTAL_FILT = 1 << 30,
117 XTAL_DRI = 1 << 28,
118 XTAL_TIMROT = 1 << 26,
119};
120
Amaury Poulydd865bc2011-12-03 15:34:40 +0000121/* Auto-Slow monitoring */
122enum imx233_as_monitor_t
123{
124 AS_CPU_INSTR = 1 << 21, /* Monitor CPU instruction access to AHB */
125 AS_CPU_DATA = 1 << 22, /* Monitor CPU data access to AHB */
126 AS_TRAFFIC = 1 << 23, /* Monitor AHB master activity */
127 AS_TRAFFIC_JAM = 1 << 24, /* Monitor AHB masters (>=3) activity */
128 AS_APBXDMA = 1 << 25, /* Monitor APBX DMA activity */
129 AS_APBHDMA = 1 << 26, /* Monitor APBH DMA activity */
130 AS_PXP = 1 << 27, /* Monitor PXP activity */
131 AS_DCP = 1 << 28, /* Monitor DCP activity */
132};
133
134enum imx233_as_div_t
135{
136 AS_DIV_1 = 0,
137 AS_DIV_2 = 1,
138 AS_DIV_4 = 2,
139 AS_DIV_8 = 3,
140 AS_DIV_16 = 4,
141 AS_DIV_32 = 5
142};
143
Amaury Poulyd0e8c352011-10-18 22:00:50 +0000144/* can use a mask of clocks */
Amaury Poulydd865bc2011-12-03 15:34:40 +0000145void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable);
146bool imx233_is_xtal_clock_enable(enum imx233_xtal_clk_t clk);
Amaury Pouly2cf33132011-06-17 22:30:58 +0000147/* only use it for non-fractional clocks (ie not for IO) */
Amaury Pouly08fb3f62011-05-01 13:02:46 +0000148void imx233_enable_clock(enum imx233_clock_t clk, bool enable);
Amaury Poulydd865bc2011-12-03 15:34:40 +0000149bool imx233_is_clock_enable(enum imx233_clock_t cl);
Amaury Pouly08fb3f62011-05-01 13:02:46 +0000150void imx233_set_clock_divisor(enum imx233_clock_t clk, int div);
Amaury Poulydd865bc2011-12-03 15:34:40 +0000151int imx233_get_clock_divisor(enum imx233_clock_t clk);
Amaury Pouly2cf33132011-06-17 22:30:58 +0000152/* call with fracdiv=0 to disable it */
153void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv);
Amaury Poulydd865bc2011-12-03 15:34:40 +0000154/* 0 means fractional dividor disable */
155int imx233_get_fractional_divisor(enum imx233_clock_t clk);
Amaury Pouly08fb3f62011-05-01 13:02:46 +0000156void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass);
Amaury Poulydd865bc2011-12-03 15:34:40 +0000157bool imx233_get_bypass_pll(enum imx233_clock_t clk);
Amaury Poulyb25d6e02011-09-14 11:50:06 +0000158void imx233_enable_usb_pll(bool enable);
Amaury Poulydd865bc2011-12-03 15:34:40 +0000159bool imx233_is_usb_pll_enable(void);
160unsigned imx233_get_clock_freq(enum imx233_clock_t clk);
161
162void imx233_set_auto_slow_divisor(enum imx233_as_div_t div);
163enum imx233_as_div_t imx233_get_auto_slow_divisor(void);
164void imx233_enable_auto_slow(bool enable);
165bool imx233_is_auto_slow_enable(void);
166void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable);
167bool imx233_is_auto_slow_monitor_enable(enum imx233_as_monitor_t monitor);
Amaury Pouly08fb3f62011-05-01 13:02:46 +0000168
169#endif /* CLKCTRL_IMX233_H */