Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 1 | /*************************************************************************** |
| 2 | * __________ __ ___. |
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
| 7 | * \/ \/ \/ \/ \/ |
| 8 | * $Id$ |
| 9 | * |
| 10 | * Copyright © 2011 by Amaury Pouly |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License |
| 14 | * as published by the Free Software Foundation; either version 2 |
| 15 | * of the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
| 18 | * KIND, either express or implied. |
| 19 | * |
| 20 | ****************************************************************************/ |
| 21 | #ifndef CLKCTRL_IMX233_H |
| 22 | #define CLKCTRL_IMX233_H |
| 23 | |
| 24 | #include "config.h" |
| 25 | #include "system.h" |
| 26 | #include "cpu.h" |
| 27 | |
| 28 | #define HW_CLKCTRL_BASE 0x80040000 |
| 29 | |
Amaury Pouly | 617d1e9 | 2011-06-30 17:31:40 +0000 | [diff] [blame] | 30 | #define HW_CLKCTRL_PLLCTRL0 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x0)) |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 31 | #define HW_CLKCTRL_PLLCTRL0__POWER (1 << 16) |
Amaury Pouly | b25d6e0 | 2011-09-14 11:50:06 +0000 | [diff] [blame] | 32 | #define HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS (1 << 18) |
| 33 | #define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BP 20 |
| 34 | #define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BM (3 << 20) |
Amaury Pouly | 617d1e9 | 2011-06-30 17:31:40 +0000 | [diff] [blame] | 35 | |
| 36 | #define HW_CLKCTRL_PLLCTRL1 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x10)) |
| 37 | |
| 38 | #define HW_CLKCTRL_CPU (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x20)) |
| 39 | #define HW_CLKCTRL_CPU__DIV_CPU_BP 0 |
| 40 | #define HW_CLKCTRL_CPU__DIV_CPU_BM 0x3f |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 41 | #define HW_CLKCTRL_CPU__INTERRUPT_WAIT (1 << 12) |
| 42 | #define HW_CLKCTRL_CPU__DIV_XTAL_BP 16 |
| 43 | #define HW_CLKCTRL_CPU__DIV_XTAL_BM (0x3ff << 16) |
| 44 | #define HW_CLKCTRL_CPU__DIV_XTAL_FRAC_EN (1 << 26) |
Amaury Pouly | 617d1e9 | 2011-06-30 17:31:40 +0000 | [diff] [blame] | 45 | #define HW_CLKCTRL_CPU__BUSY_REF_CPU (1 << 28) |
| 46 | |
| 47 | #define HW_CLKCTRL_HBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x30)) |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 48 | #define HW_CLKCTRL_HBUS__DIV_BP 0 |
| 49 | #define HW_CLKCTRL_HBUS__DIV_BM 0x1f |
| 50 | #define HW_CLKCTRL_HBUS__DIV_FRAC_EN (1 << 5) |
| 51 | #define HW_CLKCTRL_HBUS__SLOW_DIV_BP 16 |
| 52 | #define HW_CLKCTRL_HBUS__SLOW_DIV_BM (0x7 << 16) |
| 53 | #define HW_CLKCTRL_HBUS__AUTO_SLOW_MODE (1 << 20) |
Amaury Pouly | 617d1e9 | 2011-06-30 17:31:40 +0000 | [diff] [blame] | 54 | |
Amaury Pouly | e36b20c | 2011-07-03 15:18:41 +0000 | [diff] [blame] | 55 | #define HW_CLKCTRL_XBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40)) |
| 56 | #define HW_CLKCTRL_XBUS__DIV_BP 0 |
| 57 | #define HW_CLKCTRL_XBUS__DIV_BM 0x3ff |
| 58 | #define HW_CLKCTRL_XBUS__BUSY (1 << 31) |
| 59 | |
Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 60 | #define HW_CLKCTRL_XTAL (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x50)) |
| 61 | #define HW_CLKCTRL_XTAL__TIMROT_CLK32K_GATE (1 << 26) |
Amaury Pouly | d0e8c35 | 2011-10-18 22:00:50 +0000 | [diff] [blame] | 62 | #define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE (1 << 28) |
| 63 | #define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE (1 << 30) |
Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 64 | |
| 65 | #define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60)) |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 66 | #define HW_CLKCTRL_PIX__DIV_BP 0 |
Amaury Pouly | 617d1e9 | 2011-06-30 17:31:40 +0000 | [diff] [blame] | 67 | #define HW_CLKCTRL_PIX__DIV_BM 0xfff |
| 68 | |
Amaury Pouly | 2cf3313 | 2011-06-17 22:30:58 +0000 | [diff] [blame] | 69 | #define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70)) |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 70 | #define HW_CLKCTRL_SSP__DIV_BP 0 |
Amaury Pouly | 617d1e9 | 2011-06-30 17:31:40 +0000 | [diff] [blame] | 71 | #define HW_CLKCTRL_SSP__DIV_BM 0x1ff |
Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 72 | |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 73 | #define HW_CLKCTRL_EMI (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xa0)) |
| 74 | #define HW_CLKCTRL_EMI__DIV_EMI_BP 0 |
| 75 | #define HW_CLKCTRL_EMI__DIV_EMI_BM 0x3f |
| 76 | #define HW_CLKCTRL_EMI__DIV_XTAL_BP 8 |
| 77 | #define HW_CLKCTRL_EMI__DIV_XTAL_BM (0xf << 8) |
| 78 | #define HW_CLKCTRL_EMI__BUSY_REF_EMI (1 << 28) |
| 79 | #define HW_CLKCTRL_EMI__SYNC_MODE_EN (1 << 30) |
| 80 | #define HW_CLKCTRL_EMI__CLKGATE (1 << 31) |
| 81 | |
Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 82 | #define HW_CLKCTRL_CLKSEQ (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x110)) |
| 83 | #define HW_CLKCTRL_CLKSEQ__BYPASS_PIX (1 << 1) |
Amaury Pouly | 2cf3313 | 2011-06-17 22:30:58 +0000 | [diff] [blame] | 84 | #define HW_CLKCTRL_CLKSEQ__BYPASS_SSP (1 << 5) |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 85 | #define HW_CLKCTRL_CLKSEQ__BYPASS_EMI (1 << 6) |
Amaury Pouly | 617d1e9 | 2011-06-30 17:31:40 +0000 | [diff] [blame] | 86 | #define HW_CLKCTRL_CLKSEQ__BYPASS_CPU (1 << 7) |
Amaury Pouly | 2cf3313 | 2011-06-17 22:30:58 +0000 | [diff] [blame] | 87 | |
| 88 | #define HW_CLKCTRL_FRAC (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xf0)) |
| 89 | #define HW_CLKCTRL_FRAC_CPU (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf0)) |
| 90 | #define HW_CLKCTRL_FRAC_EMI (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf1)) |
| 91 | #define HW_CLKCTRL_FRAC_PIX (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf2)) |
| 92 | #define HW_CLKCTRL_FRAC_IO (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf3)) |
| 93 | #define HW_CLKCTRL_FRAC_XX__XXDIV_BM 0x3f |
| 94 | #define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6) |
| 95 | #define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7) |
Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 96 | |
| 97 | #define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120)) |
| 98 | #define HW_CLKCTRL_RESET_CHIP 0x2 |
| 99 | #define HW_CLKCTRL_RESET_DIG 0x1 |
| 100 | |
| 101 | enum imx233_clock_t |
| 102 | { |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 103 | CLK_PIX, /* freq, div, frac, bypass, enable */ |
| 104 | CLK_SSP, /* freq, div, bypass, enable */ |
| 105 | CLK_IO, /* freq, frac */ |
| 106 | CLK_CPU, /* freq, div, frac, bypass */ |
| 107 | CLK_HBUS, /* freq, div, frac */ |
| 108 | CLK_PLL, /* freq */ |
| 109 | CLK_XTAL, /* freq */ |
| 110 | CLK_EMI, /* freq */ |
| 111 | CLK_XBUS, /* freq, div */ |
Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 112 | }; |
| 113 | |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 114 | enum imx233_xtal_clk_t |
Amaury Pouly | d0e8c35 | 2011-10-18 22:00:50 +0000 | [diff] [blame] | 115 | { |
| 116 | XTAL_FILT = 1 << 30, |
| 117 | XTAL_DRI = 1 << 28, |
| 118 | XTAL_TIMROT = 1 << 26, |
| 119 | }; |
| 120 | |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 121 | /* Auto-Slow monitoring */ |
| 122 | enum imx233_as_monitor_t |
| 123 | { |
| 124 | AS_CPU_INSTR = 1 << 21, /* Monitor CPU instruction access to AHB */ |
| 125 | AS_CPU_DATA = 1 << 22, /* Monitor CPU data access to AHB */ |
| 126 | AS_TRAFFIC = 1 << 23, /* Monitor AHB master activity */ |
| 127 | AS_TRAFFIC_JAM = 1 << 24, /* Monitor AHB masters (>=3) activity */ |
| 128 | AS_APBXDMA = 1 << 25, /* Monitor APBX DMA activity */ |
| 129 | AS_APBHDMA = 1 << 26, /* Monitor APBH DMA activity */ |
| 130 | AS_PXP = 1 << 27, /* Monitor PXP activity */ |
| 131 | AS_DCP = 1 << 28, /* Monitor DCP activity */ |
| 132 | }; |
| 133 | |
| 134 | enum imx233_as_div_t |
| 135 | { |
| 136 | AS_DIV_1 = 0, |
| 137 | AS_DIV_2 = 1, |
| 138 | AS_DIV_4 = 2, |
| 139 | AS_DIV_8 = 3, |
| 140 | AS_DIV_16 = 4, |
| 141 | AS_DIV_32 = 5 |
| 142 | }; |
| 143 | |
Amaury Pouly | d0e8c35 | 2011-10-18 22:00:50 +0000 | [diff] [blame] | 144 | /* can use a mask of clocks */ |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 145 | void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable); |
| 146 | bool imx233_is_xtal_clock_enable(enum imx233_xtal_clk_t clk); |
Amaury Pouly | 2cf3313 | 2011-06-17 22:30:58 +0000 | [diff] [blame] | 147 | /* only use it for non-fractional clocks (ie not for IO) */ |
Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 148 | void imx233_enable_clock(enum imx233_clock_t clk, bool enable); |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 149 | bool imx233_is_clock_enable(enum imx233_clock_t cl); |
Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 150 | void imx233_set_clock_divisor(enum imx233_clock_t clk, int div); |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 151 | int imx233_get_clock_divisor(enum imx233_clock_t clk); |
Amaury Pouly | 2cf3313 | 2011-06-17 22:30:58 +0000 | [diff] [blame] | 152 | /* call with fracdiv=0 to disable it */ |
| 153 | void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv); |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 154 | /* 0 means fractional dividor disable */ |
| 155 | int imx233_get_fractional_divisor(enum imx233_clock_t clk); |
Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 156 | void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass); |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 157 | bool imx233_get_bypass_pll(enum imx233_clock_t clk); |
Amaury Pouly | b25d6e0 | 2011-09-14 11:50:06 +0000 | [diff] [blame] | 158 | void imx233_enable_usb_pll(bool enable); |
Amaury Pouly | dd865bc | 2011-12-03 15:34:40 +0000 | [diff] [blame] | 159 | bool imx233_is_usb_pll_enable(void); |
| 160 | unsigned imx233_get_clock_freq(enum imx233_clock_t clk); |
| 161 | |
| 162 | void imx233_set_auto_slow_divisor(enum imx233_as_div_t div); |
| 163 | enum imx233_as_div_t imx233_get_auto_slow_divisor(void); |
| 164 | void imx233_enable_auto_slow(bool enable); |
| 165 | bool imx233_is_auto_slow_enable(void); |
| 166 | void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable); |
| 167 | bool imx233_is_auto_slow_monitor_enable(enum imx233_as_monitor_t monitor); |
Amaury Pouly | 08fb3f6 | 2011-05-01 13:02:46 +0000 | [diff] [blame] | 168 | |
| 169 | #endif /* CLKCTRL_IMX233_H */ |