Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 1 | /*************************************************************************** |
| 2 | * __________ __ ___. |
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
| 7 | * \/ \/ \/ \/ \/ |
| 8 | * $Id$ |
| 9 | * |
| 10 | * Copyright (C) 2008 Rafaël Carré |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License |
| 14 | * as published by the Free Software Foundation; either version 2 |
| 15 | * of the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
| 18 | * KIND, either express or implied. |
| 19 | * |
| 20 | ****************************************************************************/ |
| 21 | |
| 22 | .text |
| 23 | |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 24 | /* AS3525 hardware registers */ |
| 25 | .set GPIOA, 0xC80B0000 |
| 26 | .set GPIOB, 0xC80C0000 |
| 27 | .set GPIOC, 0xC80D0000 |
| 28 | .set GPIOD, 0xC80E0000 |
Rafaël Carré | 66f1830 | 2010-05-17 21:57:46 +0000 | [diff] [blame] | 29 | .set CGU_PROC, 0xC80F0010 |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 30 | .set CGU_PERI, 0xC80F0014 |
Tobias Diedrich | 470be75 | 2010-06-23 06:57:53 +0000 | [diff] [blame] | 31 | .set CGU_DBOP, 0xC80F0038 |
| 32 | .set DBOP, 0xC8120000 |
Rafaël Carré | 1f251ea | 2010-03-09 16:29:38 +0000 | [diff] [blame] | 33 | .set I2C_BASE, 0xC8070000 |
| 34 | .set I2C_DATA, 0x00 |
| 35 | .set I2C_SLAD0, 0x04 |
| 36 | .set I2C_CNTRL, 0x0c |
| 37 | .set I2C_DACNT, 0x10 |
| 38 | .set I2C_CPSR0, 0x1c |
| 39 | .set I2C_CPSR1, 0x20 |
| 40 | .set I2C_IMR, 0x24 |
| 41 | .set I2C_SR, 0x30 |
| 42 | .set I2C_SADDR, 0x44 |
| 43 | .set AS3514_I2C_ADDR, 0x46 |
| 44 | .set AS3514_IRQ_ENRD0, 0x25 |
| 45 | .set PCLK, 24000000 |
| 46 | .set I2C_CLK, 400000 |
| 47 | .set I2C_PRESCALER, ((PCLK + I2C_CLK -1) / I2C_CLK) |
| 48 | .set I2C_PRESCALER_LOW, (I2C_PRESCALER & 0xff) |
| 49 | .set I2C_PRESCALER_HIGH, (I2C_PRESCALER >> 8) |
| 50 | #if I2C_PRESCALER_HIGH > 3 |
| 51 | #error i2c prescaler too big! |
| 52 | #endif |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 53 | |
| 54 | /* Vectors */ |
| 55 | |
| 56 | ldr pc, =start /* reset vector */ |
Rafaël Carré | 86f2458 | 2010-03-04 00:08:53 +0000 | [diff] [blame] | 57 | /* next vectors are unused, halt cpu */ |
| 58 | 1: b 1b |
| 59 | 1: b 1b |
| 60 | 1: b 1b |
| 61 | 1: b 1b |
| 62 | 1: b 1b |
| 63 | 1: b 1b |
| 64 | 1: b 1b |
| 65 | |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 66 | |
| 67 | /* These values are filled in by mkamsboot - don't move them from offset 0x20 */ |
| 68 | |
| 69 | uclunpack_end: .word 0 /* End of the ucl_unpack function */ |
| 70 | uclunpack_size: .word 0 /* Size in bytes of the ucl_unpack function */ |
| 71 | |
| 72 | ucl_of_end: .word 0 /* End of the ucl-compressed OF image */ |
| 73 | ucl_of_size: .word 0 /* Size in bytes of the compressed OF image */ |
| 74 | |
| 75 | ucl_rb_end: .word 0 /* End of the ucl-compressed RB image */ |
| 76 | ucl_rb_size: .word 0 /* Size in bytes of the compressed RB image */ |
| 77 | |
Rafaël Carré | b6c20c1 | 2010-02-19 14:10:26 +0000 | [diff] [blame] | 78 | ucl_dest: .word 0 /* End of our destination buffer (end of memory) */ |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 79 | |
| 80 | start: |
| 81 | /* First copy the UCL unpack function to the end of RAM */ |
| 82 | ldr r0, uclunpack_end /* Source */ |
| 83 | ldr r1, uclunpack_size /* Source length */ |
| 84 | sub r2, r0, r1 /* Source start - 1*/ |
| 85 | |
Rafaël Carré | b6c20c1 | 2010-02-19 14:10:26 +0000 | [diff] [blame] | 86 | ldr r3, ucl_dest /* Destination end */ |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 87 | |
| 88 | uclcopy: |
| 89 | ldrb r4, [r0], #-1 |
| 90 | strb r4, [r3], #-1 |
| 91 | cmp r2, r0 |
| 92 | bne uclcopy |
| 93 | |
Rafaël Carré | b6c20c1 | 2010-02-19 14:10:26 +0000 | [diff] [blame] | 94 | /* store the new destination buffer */ |
| 95 | str r3, ucl_dest |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 96 | |
| 97 | /* enable gpio clock */ |
| 98 | ldr r0, =CGU_PERI |
| 99 | ldr r1, [r0] |
| 100 | orr r1, r1, #(1<<16) |
| 101 | str r1, [r0] |
| 102 | |
| 103 | |
Rafaël Carré | b6c20c1 | 2010-02-19 14:10:26 +0000 | [diff] [blame] | 104 | /* TODO : M200V4 ? */ |
Rafaël Carré | 1f251ea | 2010-03-09 16:29:38 +0000 | [diff] [blame] | 105 | #if defined(SANSA_CLIP) || defined(SANSA_CLIPV2) |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 106 | #define USB_PIN 6 |
Rafaël Carré | c23a7cc | 2010-05-18 00:11:42 +0000 | [diff] [blame] | 107 | #elif defined(SANSA_FUZE) || defined(SANSA_E200V2) |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 108 | #define USB_PIN 3 |
| 109 | #endif |
| 110 | |
| 111 | #ifdef USB_PIN /* TODO : remove this check when we'll have an USB driver */ |
| 112 | ldr r0, =GPIOA |
| 113 | mov r1, #0 |
| 114 | str r1, [r0, #0x400] |
| 115 | ldr r1, [r0, #(4*(1<<USB_PIN))] |
| 116 | cmp r1, #0 |
| 117 | bne boot_of |
| 118 | #endif |
Rafaël Carré | 1f251ea | 2010-03-09 16:29:38 +0000 | [diff] [blame] | 119 | #if defined(SANSA_C200V2) |
| 120 | /* Instead of checking the GPIO, check the audio master IRQ_ENRD0 |
| 121 | * USB_STATUS bit on C200V2 */ |
| 122 | |
| 123 | ldr r0, =CGU_PERI |
| 124 | ldr r1, [r0] |
| 125 | /* enable i2c audio master clock */ |
| 126 | orr r1, r1, #(1<<17) |
| 127 | /* make sure 24MHz clk_main is selected */ |
| 128 | bic r1, r1, #0x7f |
| 129 | str r1, [r0] |
| 130 | |
| 131 | ldr r0, =I2C_BASE |
| 132 | /* disable i2c interrupts */ |
| 133 | mov r1, #0 |
| 134 | str r1, [r0, #I2C_IMR] |
| 135 | /* setup prescaler */ |
| 136 | mov r1, #I2C_PRESCALER_LOW |
| 137 | str r1, [r0, #I2C_CPSR0] |
| 138 | mov r1, #I2C_PRESCALER_HIGH |
| 139 | str r1, [r0, #I2C_CPSR1] |
| 140 | /* setup i2c slave address */ |
| 141 | mov r1, #(AS3514_I2C_ADDR << 1) |
| 142 | str r1, [r0, #I2C_SLAD0] |
| 143 | mov r2, #0x51 |
| 144 | str r2, [r0, #I2C_CNTRL] |
| 145 | |
| 146 | /* wait for not busy */ |
| 147 | 1: |
| 148 | ldr r1, [r0, #I2C_SR] |
| 149 | tst r1, #1 |
| 150 | bne 1b |
| 151 | |
| 152 | /* start read of irq_enrd0 */ |
| 153 | mov r1, #AS3514_IRQ_ENRD0 |
| 154 | str r1, [r0, #I2C_SADDR] |
| 155 | orr r2, r2, #(1 << 1) |
| 156 | str r2, [r0, #I2C_CNTRL] |
| 157 | mov r1, #1 |
| 158 | str r1, [r0, #I2C_DACNT] |
| 159 | |
| 160 | /* wait for transfer to finish */ |
| 161 | 1: |
| 162 | ldr r1, [r0, #I2C_DACNT] |
| 163 | cmp r1, #0 |
| 164 | bne 1b |
| 165 | |
| 166 | /* load result and test USB_STATUS bit */ |
| 167 | ldr r1, [r0, #I2C_DATA] |
| 168 | tst r1, #(1 << 3) |
| 169 | bne boot_of |
| 170 | #endif |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 171 | |
| 172 | /* Here are model specific tests, for dual boot without a computer */ |
| 173 | /* All models use left button */ |
| 174 | /* /!\ Right button for c200v2 (left button is unkwown) */ |
| 175 | |
| 176 | #ifdef SANSA_CLIP |
| 177 | .set row, (1<<5) /* enable output on C5 */ |
| 178 | .set col, (1<<0) /* read keyscan column B0 */ |
| 179 | |
| 180 | ldr r0, =GPIOC |
| 181 | mov r1, #row |
| 182 | str r1, [r0, #0x400] |
| 183 | str r1, [r0, #(4*row)] |
| 184 | |
| 185 | ldr r0, =GPIOB |
| 186 | mov r1, #0 |
| 187 | str r1, [r0, #0x400] |
| 188 | ldr r1, [r0, #(4*col)] |
| 189 | |
| 190 | cmp r1, #0 |
| 191 | bne boot_of |
| 192 | #elif defined(SANSA_CLIPV2) |
| 193 | .set row, (1<<4) /* enable output on D4 */ |
| 194 | .set col, (1<<0) /* read keyscan column D0 */ |
| 195 | |
| 196 | ldr r0, =GPIOD |
| 197 | mov r1, #((1<<5)|(1<<4)|(1<<3)) /* all rows as output */ |
| 198 | str r1, [r0, #0x400] |
| 199 | |
| 200 | /* all rows high */ |
| 201 | mov r1, #(1<<3) |
| 202 | str r1, [r0, #(4*(1<<3))] |
| 203 | mov r1, #(1<<4) |
| 204 | str r1, [r0, #(4*(1<<4))] |
| 205 | mov r1, #(1<<5) |
| 206 | str r1, [r0, #(4*(1<<5))] |
| 207 | |
| 208 | mov r1, #0 /* button row low */ |
| 209 | str r1, [r0, #(4*row)] |
| 210 | |
| 211 | mov r1, #5 /* small delay */ |
| 212 | 1: subs r1, r1, #1 |
| 213 | bne 1b |
| 214 | |
| 215 | ldr r1, [r0, #(4*col)] |
| 216 | |
| 217 | cmp r1, #0 |
| 218 | beq boot_of |
Rafaël Carré | c23a7cc | 2010-05-18 00:11:42 +0000 | [diff] [blame] | 219 | #elif defined(SANSA_E200V2) || defined(SANSA_FUZE) |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 220 | ldr r0, =GPIOC |
| 221 | mov r1, #0 |
| 222 | str r1, [r0, #0x400] |
| 223 | ldr r1, [r0, #0x20] /* read pin C3 */ |
| 224 | |
| 225 | cmp r1, #0 /* C3 = #0 means button pressed */ |
| 226 | beq boot_of |
Rafaël Carré | c23a7cc | 2010-05-18 00:11:42 +0000 | [diff] [blame] | 227 | |
| 228 | #elif defined(SANSA_FUZEV2) |
| 229 | ldr r0, =GPIOC |
| 230 | mov r1, #0 |
| 231 | str r1, [r0, #0x400] |
| 232 | ldr r1, [r0, #0x20] /* read pin C3 */ |
| 233 | |
| 234 | cmp r1, #0 /* C3 != #0 means button pressed */ |
| 235 | bne boot_of |
Thomas Martitz | f6540e8 | 2010-02-26 13:55:17 +0000 | [diff] [blame] | 236 | |
Rafaël Carré | 8b926e9 | 2010-01-13 03:05:29 +0000 | [diff] [blame] | 237 | #elif defined(SANSA_CLIPPLUS) |
Jack Halpin | de3489a | 2010-02-08 06:43:47 +0000 | [diff] [blame] | 238 | @ read pins |
| 239 | ldr r0, =GPIOC |
| 240 | ldr r1, [r0, #4*(1<<3)] @ read pin C3 "|<<" |
| 241 | |
| 242 | ldr r0, =GPIOA |
| 243 | ldr r2, [r0, #4*(1<<1)] @ read pin A1 "Home" |
| 244 | |
| 245 | orr r2, r2, r1 @ c3 || A1 |
| 246 | |
Jack Halpin | de3489a | 2010-02-08 06:43:47 +0000 | [diff] [blame] | 247 | cmp r2, #0 @ test input from pins |
| 248 | bne boot_of @ branch directly to OF if either pin high |
Rafaël Carré | 66f1830 | 2010-05-17 21:57:46 +0000 | [diff] [blame] | 249 | |
| 250 | |
Rafaël Carré | c23a7cc | 2010-05-18 00:11:42 +0000 | [diff] [blame] | 251 | #elif defined(SANSA_C200V2) |
Tobias Diedrich | 470be75 | 2010-06-23 06:57:53 +0000 | [diff] [blame] | 252 | .set BUTTON_LEFT, (1<< 2) |
| 253 | .set BUTTON_DOWN, (1<< 3) |
| 254 | .set BUTTON_SELECT, (1<< 4) |
| 255 | .set BUTTON_UP, (1<< 5) |
| 256 | .set BUTTON_RIGHT, (1<< 6) |
| 257 | .set BUTTON_HOLD, (1<<12) |
Rafaël Carré | c23a7cc | 2010-05-18 00:11:42 +0000 | [diff] [blame] | 258 | |
Tobias Diedrich | 470be75 | 2010-06-23 06:57:53 +0000 | [diff] [blame] | 259 | ldr r0, =CGU_DBOP |
| 260 | mov r1, #(1<<3) @ DBOP freq = PCLK, clock enabled |
| 261 | str r1, [r0] |
| 262 | |
| 263 | @ AFSEL needs to be set for this to work |
| 264 | ldr r2, =GPIOB |
| 265 | mov r1, #0xc |
| 266 | str r1, [r2, #0x420] @ GPIOB_AFSEL |
| 267 | ldr r2, =GPIOC |
| 268 | mov r1, #0xff |
| 269 | str r1, [r2, #0x420] @ GPIOC_AFSEL |
| 270 | |
| 271 | ldr r0, =DBOP |
| 272 | @ TIMPOL doesn't matter here since we don't need |
| 273 | @ the control signals. |
| 274 | |
| 275 | @ 16 bit data width |
| 276 | @ enable write |
| 277 | @ tri-state output |
| 278 | ldr r1, =0x00091000 |
| 279 | str r1, [r0, #8] @ DBOP_CTRL |
| 280 | |
| 281 | ldr r1, =0xf0ff @ precharge |
| 282 | str r1, [r0, #0x10] @ DBOP_DOUT |
| 283 | |
| 284 | 2: ldr r1, [r0, #0xc] @ DOBP_STAT |
| 285 | ands r1, r1, #(1<<10) |
| 286 | beq 2b @ make sure fifo is empty |
| 287 | |
| 288 | @ 16 bit data width |
| 289 | @ start read |
| 290 | @ tri-state output |
| 291 | @ strobe time 31 |
| 292 | ldr r1, =0x0008901f |
| 293 | str r1, [r0, #8] @ DBOP_CTRL |
| 294 | |
| 295 | 3: ldr r1, [r0, #0xc] @ DOBP_STAT |
| 296 | ands r1, r1, #(1<<16) |
| 297 | beq 3b @ wait for valid data |
| 298 | |
| 299 | ldrh r1, [r0, #0x14] @ DBOP_DIN |
| 300 | |
| 301 | tst r1, #BUTTON_LEFT @ boot of? |
Rafaël Carré | c23a7cc | 2010-05-18 00:11:42 +0000 | [diff] [blame] | 302 | beq boot_of |
| 303 | #elif defined(SANSA_M200V4) |
| 304 | .set row, (1<<5) /* enable output on A5 */ |
| 305 | .set col, (1<<0) /* read keyscan column A0 */ |
| 306 | |
| 307 | ldr r0, =GPIOA |
| 308 | mov r1, #row |
| 309 | str r1, [r0, #0x400] |
| 310 | str r1, [r0, #(4*row)] |
| 311 | |
| 312 | ldr r2, [r0, #(4*col)] |
| 313 | |
| 314 | /* check value read (1 means button pressed) */ |
| 315 | cmp r2, #0 |
| 316 | bne boot_of |
| 317 | #else |
| 318 | #error No target-specific key check defined! |
| 319 | #endif |
| 320 | |
| 321 | #if defined(SANSA_CLIPPLUS) || defined(SANSA_FUZEV2) |
| 322 | /* Check for USB after buttons because I trust more the GPIO code than |
| 323 | * the i2c code. |
| 324 | * Also it seems we need to wait a bit before detecting USB connection |
| 325 | * on those models, but not on c200v2 |
| 326 | */ |
| 327 | |
Rafaël Carré | 66f1830 | 2010-05-17 21:57:46 +0000 | [diff] [blame] | 328 | |
| 329 | ldr r0, =CGU_PROC |
| 330 | mov r1, #0 |
| 331 | str r1, [r0] @ fclk = 24MHz |
| 332 | |
| 333 | ldr r0, =CGU_PERI |
| 334 | ldr r1, [r0] |
| 335 | /* enable i2c audio master clock */ |
| 336 | orr r1, r1, #(1<<17) |
| 337 | /* pclk = fclk = 24MHz */ |
| 338 | bic r1, r1, #0x7f |
| 339 | str r1, [r0] |
| 340 | |
| 341 | ldr r0, =I2C_BASE |
| 342 | /* disable i2c interrupts */ |
| 343 | mov r1, #0 |
| 344 | str r1, [r0, #I2C_IMR] |
| 345 | /* setup prescaler */ |
| 346 | mov r1, #I2C_PRESCALER_LOW |
| 347 | str r1, [r0, #I2C_CPSR0] |
| 348 | mov r1, #I2C_PRESCALER_HIGH |
| 349 | str r1, [r0, #I2C_CPSR1] |
| 350 | /* setup i2c slave address */ |
| 351 | mov r1, #(AS3514_I2C_ADDR << 1) |
| 352 | str r1, [r0, #I2C_SLAD0] |
| 353 | mov r2, #0x51 |
| 354 | str r2, [r0, #I2C_CNTRL] |
| 355 | |
| 356 | /* wait for not busy */ |
| 357 | 1: |
| 358 | ldr r1, [r0, #I2C_SR] |
| 359 | tst r1, #1 |
| 360 | bne 1b |
| 361 | |
| 362 | /* wait a bit (~100ms) else detection fails */ |
| 363 | mov r1, #0x80000 |
| 364 | 1: subs r1, r1, #1 |
| 365 | bne 1b |
| 366 | |
| 367 | /* start read of irq_enrd0 */ |
| 368 | mov r1, #AS3514_IRQ_ENRD0 |
| 369 | str r1, [r0, #I2C_SADDR] |
| 370 | orr r2, r2, #(1 << 1) |
| 371 | str r2, [r0, #I2C_CNTRL] |
| 372 | mov r1, #1 |
| 373 | str r1, [r0, #I2C_DACNT] |
| 374 | |
| 375 | /* wait for transfer to finish */ |
| 376 | 1: |
| 377 | ldr r1, [r0, #I2C_DACNT] |
| 378 | cmp r1, #0 |
| 379 | bne 1b |
| 380 | |
| 381 | /* load result and test USB_STATUS bit */ |
| 382 | ldr r1, [r0, #I2C_DATA] |
| 383 | tst r1, #(1 << 3) |
| 384 | bne boot_of |
| 385 | |
| 386 | |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 387 | #endif |
| 388 | |
| 389 | |
| 390 | /* The dualboot button was not held, so we boot rockbox */ |
| 391 | ldr r0, ucl_rb_end /* Address of compressed image */ |
| 392 | ldr r1, ucl_rb_size /* Compressed size */ |
| 393 | b decompress |
| 394 | |
| 395 | boot_of: |
| 396 | ldr r0, ucl_of_end /* Address of compressed image */ |
| 397 | ldr r1, ucl_of_size /* Compressed size */ |
| 398 | |
| 399 | |
| 400 | decompress: |
| 401 | /* At this point: */ |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 402 | /* r0 = source_end for UCL image to copy */ |
| 403 | /* r1 = size of UCL image to copy */ |
| 404 | |
Rafaël Carré | b6c20c1 | 2010-02-19 14:10:26 +0000 | [diff] [blame] | 405 | ldr r3, ucl_dest |
| 406 | add r5, r3, #2 /* r5 is entry point of copy of uclunpack */ |
| 407 | /* function, plus one (for thumb mode */ |
| 408 | |
Rafaël Carré | 96165ab | 2009-05-28 18:27:08 +0000 | [diff] [blame] | 409 | sub r4, r3, r1 /* r4 := destination_start - 1 */ |
| 410 | |
| 411 | fw_copy: |
| 412 | ldrb r2, [r0], #-1 |
| 413 | strb r2, [r3], #-1 |
| 414 | cmp r3, r4 /* Stop when we reached dest_start-1 */ |
| 415 | bne fw_copy |
| 416 | |
| 417 | /* Call the ucl decompress function, which will branch to 0x0 */ |
| 418 | /* on completion */ |
| 419 | add r0, r3, #1 /* r0 := Start of compressed image */ |
| 420 | /* r1 already contains compressed size */ |
| 421 | mov r2, #0 /* r2 := Destination for unpacking */ |
| 422 | bx r5 /* Branch to uclunpack, switching to thumb */ |
| 423 | |
| 424 | /* never reached : uclunpack will branch to the reset vector (0x0) */ |