blob: c959bf272dc0e9e5a07f518554276198ce110ad1 [file] [log] [blame]
Daniel Stenberg762a6c62004-09-03 13:16:19 +00001#include "config.h"
2
Daniel Stenberg32cd5552004-09-03 13:02:16 +00003ENTRY(start)
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +00004
Christian Gmeinerc6ff1f52005-07-18 12:40:29 +00005#ifdef CPU_COLDFIRE
Linus Nielsen Feltzing63cf21d2005-01-28 13:19:01 +00006OUTPUT_FORMAT(elf32-m68k)
Jens Arnold2bbacf82008-04-29 06:19:32 +00007STARTUP(target/coldfire/crt0.o)
Daniel Ankers41997d32006-08-31 19:45:05 +00008#elif defined(CPU_PP)
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +00009OUTPUT_FORMAT(elf32-littlearm)
Rafaël Carré7ef13ee2012-01-03 04:44:27 +000010STARTUP(target/arm/pp/crt0-pp.o)
Daniel Ankers41997d32006-08-31 19:45:05 +000011#elif defined(CPU_ARM)
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +000012OUTPUT_FORMAT(elf32-littlearm)
Jens Arnold2bbacf82008-04-29 06:19:32 +000013STARTUP(target/arm/crt0.o)
Daniel Ankers41997d32006-08-31 19:45:05 +000014#elif CONFIG_CPU == SH7034
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +000015OUTPUT_FORMAT(elf32-sh)
Jens Arnold2bbacf82008-04-29 06:19:32 +000016STARTUP(target/sh/crt0.o)
Daniel Ankers41997d32006-08-31 19:45:05 +000017#else
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +000018OUTPUT_FORMAT(elf32-sh)
Jens Arnold2bbacf82008-04-29 06:19:32 +000019STARTUP(crt0.o)
Daniel Ankers41997d32006-08-31 19:45:05 +000020#endif
21
Jens Arnold09780262005-01-12 01:25:19 +000022
Dave Chapmane4523832005-02-15 14:00:37 +000023#if MEMORYSIZE >= 32
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +000024#define PLUGINSIZE PLUGIN_BUFFER_SIZE
Dave Chapmane4523832005-02-15 14:00:37 +000025#else
Jens Arnold09780262005-01-12 01:25:19 +000026#define PLUGINSIZE 0x8000
Dave Chapmane4523832005-02-15 14:00:37 +000027#endif
Jens Arnold09780262005-01-12 01:25:19 +000028
Linus Nielsen Feltzing63cf21d2005-01-28 13:19:01 +000029
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +000030#ifdef IRIVER_H100_SERIES
31#define CODECSIZE CODEC_SIZE
Linus Nielsen Feltzing1c40d3c2005-04-20 06:48:17 +000032#define DRAMORIG 0x31000000
Linus Nielsen Feltzing63cf21d2005-01-28 13:19:01 +000033#define IRAMORIG 0x10000000
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +000034#define IRAMSIZE 0xc000
35#define FLASHORIG 0x00100028
36#define FLASHSIZE 0x000eff80
Linus Nielsen Feltzing63cf21d2005-01-28 13:19:01 +000037#else
38#define DRAMORIG 0x09000000
Jens Arnold09780262005-01-12 01:25:19 +000039#define IRAMORIG 0x0f000000
40#define IRAMSIZE 0x1000
41#define FLASHORIG 0x02000000 + ROM_START
42#define FLASHSIZE 256K - ROM_START
Linus Nielsen Feltzing63cf21d2005-01-28 13:19:01 +000043#endif
Jens Arnold09780262005-01-12 01:25:19 +000044
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +000045#ifdef CODECSIZE
46#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
47/* Where the codec buffer ends, and the plugin buffer starts */
48#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
49#else
50#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE
51/* Where the audio buffer ends, and the plugin buffer starts */
52#define ENDADDR ENDAUDIOADDR
53#endif
54
55/* End of the audio buffer, where the codec/plugin buffer starts */
56#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
Marcin Bukat21d026d2014-01-18 23:11:25 +010057#define CODECORIG ENDAUDIOADDR
58
Daniel Stenberg32cd5552004-09-03 13:02:16 +000059MEMORY
60{
Jens Arnold09780262005-01-12 01:25:19 +000061 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
62 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
63 FLASH : ORIGIN = FLASHORIG, LENGTH = FLASHSIZE
Daniel Stenberg32cd5552004-09-03 13:02:16 +000064}
Marcin Bukat21d026d2014-01-18 23:11:25 +010065
Daniel Stenberg32cd5552004-09-03 13:02:16 +000066SECTIONS
67{
Jörg Hohensohn13be9f12005-08-23 07:26:40 +000068 .flashheader :
69 {
70 /* place flash link address first, so the plugin can check */
71 LONG(FLASHORIG);
72 /* followed by the start address, the first vector takes care of this. */
73 /* If we ever place the table elsewhere, put a constant here. */
74 } > FLASH
75
Daniel Stenberg32cd5552004-09-03 13:02:16 +000076 .vectors :
77 {
78 _datacopy = .;
79 } > FLASH
80
81 .data : AT ( _datacopy )
82 {
Linus Nielsen Feltzingbd42d312005-03-31 08:47:02 +000083 loadaddress = .;
84 _loadaddress = .;
Daniel Stenberg32cd5552004-09-03 13:02:16 +000085 _datastart = .;
Boris Gjeneroca9111e2011-12-18 06:43:08 +000086 KEEP(*(.resetvectors));
87 KEEP(*(.vectors));
Linus Nielsen Feltzing63cf21d2005-01-28 13:19:01 +000088 . = ALIGN(0x200);
Marcin Bukatb3abcb82014-01-20 10:42:02 +010089#ifdef HAVE_INIT_ATTR
90 *(.initdata*)
91#endif
Boris Gjenero0efabb32011-12-18 07:09:00 +000092 *(.data*)
Daniel Stenberg32cd5552004-09-03 13:02:16 +000093 . = ALIGN(0x4);
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +000094 _dataend = .;
Daniel Stenberg678090a2004-09-06 07:05:12 +000095 . = ALIGN(0x10); /* Maintain proper alignment for .text section */
Daniel Stenberg32cd5552004-09-03 13:02:16 +000096 } > DRAM
97
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +000098 /DISCARD/ :
99 {
100 *(.eh_frame)
101 }
102
Daniel Stenberg678090a2004-09-06 07:05:12 +0000103 /* TRICK ALERT! Newer versions of the linker don't allow output sections
104 to overlap even if one of them is empty, so advance the location pointer
105 "by hand" */
106 .text LOADADDR(.data) + SIZEOF(.data) :
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000107 {
108 *(.init.text)
Marcin Bukat21d026d2014-01-18 23:11:25 +0100109 KEEP(*(.startup*));
Marcin Bukatb3abcb82014-01-20 10:42:02 +0100110#ifdef HAVE_INIT_ATTR
111 /* all this symbols are set to the same address so .init copy loop
112 will be skiped in crt0.S */
113 _initstart = .;
114 _initend = .;
115 _initcopy = .;
116 *(.init*)
117#endif
Boris Gjenero0efabb32011-12-18 07:09:00 +0000118 *(.text*)
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000119 . = ALIGN(0x4);
120 } > FLASH
121
122 .rodata :
123 {
Boris Gjenero0efabb32011-12-18 07:09:00 +0000124 *(.rodata*)
Linus Nielsen Feltzing63cf21d2005-01-28 13:19:01 +0000125 *(.rodata.str1.1)
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000126 *(.rodata.str1.4)
127 . = ALIGN(0x4);
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000128 _iramcopy = .;
129 } > FLASH
130
Linus Nielsen Feltzing63cf21d2005-01-28 13:19:01 +0000131 .iram IRAMORIG : AT ( _iramcopy )
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000132 {
133 _iramstart = .;
134 *(.icode)
Jens Arnoldabd9f832005-10-19 19:35:24 +0000135 *(.irodata)
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000136 *(.idata)
137 _iramend = .;
138 } > IRAM
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000139
Jens Arnoldabd9f832005-10-19 19:35:24 +0000140 .ibss (NOLOAD) :
141 {
142 _iedata = .;
143 *(.ibss)
144 . = ALIGN(0x4);
145 _iend = .;
146 } > IRAM
147
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000148 .stack :
149 {
150 *(.stack)
151 _stackbegin = .;
Linus Nielsen Feltzing63cf21d2005-01-28 13:19:01 +0000152 stackbegin = .;
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000153 . += 0x2000;
154 _stackend = .;
Linus Nielsen Feltzing63cf21d2005-01-28 13:19:01 +0000155 stackend = .;
Miika Pekkarinenee4caec2007-01-08 19:19:23 +0000156#if IRAMSIZE > 0x1000
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000157 } > IRAM
Miika Pekkarinenee4caec2007-01-08 19:19:23 +0000158#else
159 } > DRAM
160#endif
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000161
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000162#ifdef CPU_COLDFIRE
163 .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram):
164#else
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000165 .bss :
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000166#endif
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000167 {
168 _edata = .;
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000169 *(.bss*)
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000170 *(COMMON)
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000171 . = ALIGN(0x4);
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000172 _end = .;
173 } > DRAM
174
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000175 .audiobuf ALIGN(4):
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000176 {
Linus Nielsen Feltzingd34865a2005-04-05 11:33:58 +0000177 _audiobuffer = .;
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000178 audiobuffer = .;
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000179 } > DRAM
180
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000181#ifdef CODECSIZE
182 .audiobufend ENDAUDIOADDR:
183#else
Linus Nielsen Feltzingd34865a2005-04-05 11:33:58 +0000184 .audiobufend ENDADDR:
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000185#endif
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000186 {
Linus Nielsen Feltzingd34865a2005-04-05 11:33:58 +0000187 _audiobufend = .;
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000188 audiobufend = .;
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000189 } > DRAM
190
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000191#ifdef CODECSIZE
192 .codec ENDAUDIOADDR:
193 {
194 codecbuf = .;
195 _codecbuf = .;
196 }
197#endif
198
Jens Arnold09780262005-01-12 01:25:19 +0000199 .plugin ENDADDR:
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000200 {
201 _pluginbuf = .;
Miika Pekkarinenb1af4e62007-01-08 18:21:12 +0000202 pluginbuf = .;
Daniel Stenberg32cd5552004-09-03 13:02:16 +0000203 }
204}