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Barry Wardell18cfe432006-08-20 23:05:47 +00001/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 by Barry Wardell
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#include "config.h"
20#include "cpu.h"
21#include "system.h"
22#include "kernel.h"
23#include "thread.h"
24#include "adc.h"
25
Barry Wardelle367b052006-08-22 20:17:09 +000026static unsigned short adcdata[NUM_ADC_CHANNELS];
27
28/* Scan ADC so that adcdata[channel] gets updated */
Barry Wardell18cfe432006-08-20 23:05:47 +000029unsigned short adc_scan(int channel)
30{
Barry Wardelle367b052006-08-22 20:17:09 +000031 unsigned int adc_data_1;
32 unsigned int adc_data_2;
33
34 /* Initialise */
35 ADC_ADDR=0x130;
36 ADC_STATUS=0; /* 4 bytes, 1 per channel. Each byte is 0 if the channel is
37 off, 0x40 if the channel is on */
38
39 /* Enable Channel */
40 ADC_ADDR |= (0x1000000<<channel);
41
42 /* Start? */
43 ADC_ADDR |= 0x20000000;
44 ADC_ADDR |= 0x80000000;
45
46 /* Wait 50ms for things to settle */
47 sleep(HZ/20);
48
49 /* ADC_DATA_1 and ADC_DATA_2 are both four bytes, one byte per channel.
50 For each channel, ADC_DATA_1 stores the 8-bit msb, ADC_DATA_2 stores the
51 2-bit lsb (in bits 0 and 1). Each channel is 10 bits total. */
52 adc_data_1 = ((ADC_DATA_1 >> (8*channel)) & 0xff);
53 adc_data_2 = ((ADC_DATA_2 >> (8*channel+6)) & 0x3);
54
55 adcdata[channel] = (adc_data_1<<2 | adc_data_2);
56
57 return adcdata[channel];
Barry Wardell18cfe432006-08-20 23:05:47 +000058}
59
Barry Wardelle367b052006-08-22 20:17:09 +000060/* Read 10-bit channel data */
Barry Wardell18cfe432006-08-20 23:05:47 +000061unsigned short adc_read(int channel)
62{
Barry Wardelle367b052006-08-22 20:17:09 +000063 return adcdata[channel];
64}
65
66static int adc_counter;
67
68static void adc_tick(void)
69{
70 if(++adc_counter == HZ)
71 {
72 adc_counter = 0;
73 adc_scan(ADC_BATTERY);
74 adc_scan(ADC_UNKNOWN_1);
75 adc_scan(ADC_UNKNOWN_2);
76 adc_scan(ADC_SCROLLPAD);
77 }
Barry Wardell18cfe432006-08-20 23:05:47 +000078}
79
80void adc_init(void)
81{
Barry Wardelle367b052006-08-22 20:17:09 +000082 /* Enable ADC */
83 ADC_ENABLE_ADDR |= ADC_ENABLE;
84
85 /* Initialise */
86 ADC_INIT=0;
87 ADC_ADDR=0x130;
88 ADC_STATUS=0;
89
90 /* Enable Channels 1-4 */
91 ADC_ADDR |= 0x1000000;
92 ADC_ADDR |= 0x2000000;
93 ADC_ADDR |= 0x4000000;
94 ADC_ADDR |= 0x8000000;
95
96 /* Start? */
97 ADC_ADDR |= 0x20000000;
98 ADC_ADDR |= 0x80000000;
99
100 /* Wait 50ms for things to settle */
101 sleep(HZ/20);
102
103 tick_add_task(adc_tick);
Barry Wardell18cfe432006-08-20 23:05:47 +0000104}